A Technological Review on Quantum Ballistic Transport Model Based Silicon Nanowire Field Effect Transistors for Circuit Simulation and Design (original) (raw)

A Simulation Study of Silicon Nanowire Field Effect Transistors (FETs)

2007

Silicon planar MOSFETs are approaching their scaling limits. New device designs are being explored to replace the existing planar technology. Among the possible new device designs are Double Gate (DG) FETs, FinFETs, Tri-Gate FETs and Omega-Gate FETs. The Silicon Nanowire Gate All Around (GAA) FET stands out as one of the

A compact model of silicon-based nanowire MOSFETs for circuit simulation and design

Electron Devices, …, 2008

A silicon-based nanowire FET (SNWT) compact model is developed for circuit simulation. Starting from the solution of Poisson's equation, an accurate inversion charge expression is derived for SNWTs with arbitrary body doping concentration. The drain current, transconductance, output conductance, terminal charges, and capacitances are then calculated based on fundamental device physics. Short-channel and quantum effects have been included in the model in a self-consistent way. Comparison between the numerical simulation and analytical calculation shows that the proposed model is valid for all operation regions of SNWTs with different dimensions and channel doping. The model has been implemented in circuit simulators by Verilog-A, and its application in circuit simulation is also demonstrated.

A Compact Model of Silicon-Based Nanowire Field Effect Transistor for Circuit Simulation and Design

ArXiv, 2014

As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits; many novel device structures are being extensively explored. Among them, the silicon nanowire transistor (SNWT) has attracted broad attention. To understand device physics in depth and to assess the performance limits of SNWTs, simulation is becoming increasingly important. The objectives of this work are: 1) to theoretically explore the essential physics of SNWTs (e.g., electrostatics, transport and band structure) by performing computer-based simulations, and 2) to assess the performance limits and scaling potentials of SNWTs and to address the SNWT design issues. The computer based simulations carried out are essentially based on DFT using NEGF formalism. A silicon nanowire has been modeled as PN diode (Zener Diode), PIN diode, PIP & NIN diode configurations by selectively doping the nanowire and simulated by biasing one end of the nanowire to ground and sweeping ...

Quantum simulation study of gate-all-around (GAA) silicon nanowire transistor and double gate metal oxide semiconductor field effect transistor (DG MOSFET)

International Journal of the Physical Sciences, 2012

In this paper, electrical characteristics of the double gate metal oxide semiconductor field effect transistor (DG MOSFET) and that of gate all around silicon nanowire transistor (GAA SNWT) have been investigated. We have evaluated the variations of the threshold voltage, the subthreshold slope, draininduced barrier lowering, ON and OFF state currents when channel length decreases. Quantum mechanical transport approach based on non-equilibrium Green's function method (NEGF) has been performed in the frame work of effective mass theory with taking into account exchange-correlation effects. Its simulation consists of solutions of the three dimensional Poisson's equation, two dimensional Schrodinger equation on the cross section plane, and also transport equation. We have shown that for lengths smaller than 15 nm, short channel effects dominate. When the dimensions become smaller, interelectronic distance decreases and the interaction between electrons and also exchange correlation effects increase. We have also demonstrated that short channel effects are decreased using the device which has a good control of gate.

Correlation between Gate Length, Geometry and Electrostatic Driven Performance in Ultra-Scaled Silicon Nanowire Transistors

—In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six different cross-section shapes. However for all devices the cross-sectional area is kept constant in order to provide fair comparison. Additionally we have expanded the computational experiment by including different gate length and gate materials for each of these six Si NWTs. As a result we have established a correlation between the mobile charge distribution in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also have been investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrödinger equation, which is indeed mandatory for nanowires with such ultra-scale dimensions.

Comparative Study of Multi-gate Nanowire Field Effect Transistor

Journal of Nanotechnology and Nano-Engineering , 2019

A silicon multi-gate nanowire simulation is presented in this paper. The simulation studies are conducted based on electrical parameters such as Current-Voltage (I-V) characteristics, Mid-channel conduction band profile and mid-channel charge density profile using Nanohub Multi-gate Nanowire FET simulator. These characterization studies are performed to investigate the performance of silicon nanowire based on different gate arrangements in the device. We have simulated the silicon nanowire field effect transistors (FETs) with multiple gates such as double, tri, pi, omega and Gate-all-around gate structures using Nanohub simulation software. Effects of varying different parameters (such as Vgs and channel distance) in different devices and their effects are also presented.

Potential and Quantum Threshold Voltage Modeling of Gate-All-Around Nanowire MOSFETs

Active and Passive Electronic Components, 2013

An improved physics-based compact model for a symmetrically biased gate-all-around (GAA) silicon nanowire transistor is proposed. Short channel effects and quantum mechanical effects caused by the ultrathin silicon devices are considered in modelling the threshold voltage. Device geometrics play a very important role in multigate devices, and hence their impact on the threshold voltage is also analyzed by varying the height and width of silicon channel. The inversion charge and electrical potential distribution along the channel are expressed in their closed forms. The proposed model shows excellent accuracy with TCAD simulations of the device in the weak inversion regime.

Performance evaluation of ballistic silicon nanowire transistors with atomic-basis dispersion relations

Applied Physics …, 2005

In this letter, we explore the bandstructure effects on the performance of ballistic silicon nanowire transistors (SNWTs). The energy dispersion relations for silicon nanowires are evaluated with an sp 3 d 5 s * tight binding model. Based on the calculated dispersion relations, the ballistic currents for both n-type and p-type SNWTs are evaluated by using a semi-numerical ballistic model. For large diameter nanowires, we find that the ballistic p-SNWT delivers half the ON-current of a ballistic n-SNWT. For small diameters, however, the ON-current of the p-type SNWT approaches that of its n-type counterpart. Finally, the carrier injection velocity for SNWTs is compared with those for planar metal-oxide-semiconductor field-effect transistors, clearly demonstrating the impact of quantum confinement on the performance limits of SNWTs. PACS numbers: 85.35.Be and 73.63.Nm

A proposal and simulation analysis for a novel architecture of gate-all-around polycrystalline silicon nanowire field effect transistor

International Journal of Electrical and Computer Engineering (IJECE), 2024

A proposal for a novel gate-all-around (GAA) polycrystalline silicon nanowire (poly-SiNW) field effect transistor (FET) is presented and discussed in this paper. The device architecture is based on the realization of poly-SiNW in a V-shaped cavity obtained by tetra methyl ammonium hydroxide (TMAH) etch of monocrystalline silicon (100). The device's behavior is simulated using Silvaco commercial software, including the density of states (DOS) model described by the double exponential distribution of acceptor trap density within the gap. The electric field, potential, and free electron concentration are analyzed in different nanowire regions to investigate the device's performance. The results show good performance despite the high density of deep states in poly-SiNW. This can be explained by the strong electric field caused by the corner effect in the nanowire, which favors the ionization of the acceptor traps and increases the free electron concentration.