Encoding Schemes For Reduction Of Power Dissipation, Crosstalk And Delay In VLSI Interconnects: A Review (original) (raw)
Related papers
A bus encoding method for crosstalk and power reduction in RC coupled VLSI interconnects
The performance factors such as propagation delay, power dissipation and crosstalk in RC modelled interconnects are major design issues for the System on-chip (SoC) designs in current Deep Submicron (DSM) era. The crosstalk effect is a consequence of coupling and switching activities that is encountered when there is a transition as compared to previous state of wire and or when there are transitions in adjacent wires. Therefore, minimization or elimination of switching and coupling activities is crucial in enhancing the performance of SoC designs. There are several methods for the reduction of power dissipation, crosstalk and delay. The encoding method is most effective and popular method for enhancing the behaviour of on-chip buses. This paper proposes encoding scheme to achieve overall reduction in transitions. The reduction in transition improves the performance in terms of reduced power dissipation, coupling activity and delay in on-chip buses. This encoding method is implemented using VHDL. The result evidently demonstrates reduction in transitions which consequently improves the overall performance of on-chip buses.
A New Bus Coding Technique to minimize crosstalk in VLSI Bus
In DSM technology, minimizing the propagation delay and power consumption on buses is the most important design objective in system-on-chip design. In particular, the coupling effects between wires on the bus that can cause serious problems such as crosstalk delay, noise and power consumption. This paper proposes a technique which reduces power consumption data buses which are fed to a DSP/Communication device. The proposed coding technique reduces the transition activity in the input signals and will consequently result in the reduction of power consumption. A new bus coding technique has been proposed to achieve less power reduction in transmission. SPICE simulations are carried out for interconnect lines of different dimensions at various technology nodes (180, 130, 90 and 65 nm). The proposed model reduces the power consumption by upto 35%.
Analysis, reduction and avoidance of crosstalk on VLSI chips
As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on-chip timing and even functionality. A method is presented to analyze crosstalk while taking into account timing relationship and timing criticality between coupling wires. The method is based upon the geometrical layout of the wires (adjacency), the signal slopes on the wires (circuit driving capability) and timing considerations. Based on these wire characteristics, a pattern driven routing tool imbeds the crosstalk critical nets in non-adjacent wiring tracks for crosstalk avoidance. The pattern driven routing capability may also be used for rerouting crosstalk critical nets of an already existing routing for crosstalk reduction. The crosstalk analysis and the routing tool described in this paper were used in three generations of VLSI processor chip designs for IBM's S/390 computers, always resulting in crosstalk-resistant hardware.
A Review on Crosstalk Avoidance and Minimization in VLSI Systems
2015
With advancements in VLSI fabrication technology, interconnecting wires are being placed in closer proximity while circuits are starting to operate at higher frequencies. Thus, reduction in crosstalk between interconnects becomes an important consideration for VLSI physical design. In this paper, we have reviewed the effects and impact that crosstalk has on the performance and reliability of VLSI circuits and systems. We have also presented a concise but informative review on the various methods that researchers worldwide are implementing for a priori crosstalk avoidance or a posteriori crosstalk minimization in VLSI systems from the point of view of fabrication over the past few decades.
High density chips have introduced problems like crosstalk noise and power dissipation. The mismatching in transition time of the inputs occurs because different lengths of interconnects lead to different parasitic values. This paper presents the analysis of the effect of equal and unequal (mismatched) transition time of inputs on power dissipation in coupled interconnects. Further, the effect of signal skew on transition time is analysed. To demonstrate the effects, a model of two distributed RLC lines coupled capacitively and inductively is taken into consideration. Each interconnect line is 4mm long and terminated by capacitive load of 30fF. The analysis is carried out for simultaneously switching lines. The results are obtained through SPICE simulations and waveforms are generated.
Crosstalk in VLSI interconnections
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000
We address the problem of crosstalk computation and reduction using circuit and layout techniques in this paper. We provide easily computable expressions for crosstalk amplitude and pulse width in resistive, capacitively coupled lines. The expressions hold for nets with arbitrary number of pins and of arbitrary topology under any specified input excitation. Experimental results show that the average error is about 10% and the maximum error is less than 20%. The expressions are used to motivate circuit techniques, such as transistor sizing, and layout techniques, such as wire ordering and wire width optimization to reduce crosstalk.
An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects
In VLSI interconnect buffers are used to restore the signal level affected by the parasitics. However buffers have a certain switching time that contributes to overall signal delay. Further the transitions that occur in interconnects also contribute to crosstalk delay. Thus the overall delay in interconnects is due to combined effect of both buffer and crosstalk delay. In this work a replacement of buffers with Schmitt trigger is proposed for the same purpose of signal restoration. Due to lower threshold voltage of Schmitt trigger signal can rise early and the large noise margin of Schmitt trigger helps in reducing the noise glitches as well. Simulation results shows that the Schmitt trigger approach gives 20% delay reduction as compared to 10.4% in case of buffers.
Efficient RC low-power bus encoding methods for crosstalk reduction
Integration, the VLSI Journal, 2011
In on-chip buses, the RC crosstalk effect leads to serious problems, such as wire propagation delay and dynamic power dissipation. This paper presents two efficient bus-coding methods. The proposed methods simultaneously reduce more dynamic power dissipation and wire propagation delay than existing bus encoding methods. Our methods also reduce more total power consumption than other encoding methods. Simulation results show that the proposed method I reduces coupling activity by 26.7-38.2% and switching activity by 3.7%-7% on 8-bit to 32-bit data buses, respectively. The proposed method II reduces coupling activity by 27.5-39.1% and switching activity by 5.3-9% on 8-bit to 32-bit data buses, respectively. Both the proposed methods reduce dynamic power by 23.9-35.3% on 8-bit to 32-bit data buses and total propagation delay by up to 30.7-44.6% on 32-bit data buses, and eliminate the Type-4 coupling. Our methods also reduce total power consumption by 23.6-33.9%, 23.9-34.3%, and 24.1-34.6% on 8-bit to 32-bit data buses with the 0.18, 0.13, and 0.09 mm technologies, respectively.
IJERT-Error Correction And Crosstalk Avoidance Techniques In On-Chip VLSI Interconnects
International Journal of Engineering Research and Technology (IJERT), 2012
https://www.ijert.org/error-correction-and-crosstalk-avoidance-techniques-in-on-chip-vlsi-interconnects https://www.ijert.org/research/error-correction-and-crosstalk-avoidance-techniques-in-on-chip-vlsi-interconnects-IJERTV1IS8502.pdf In On-Chip VLSI interconnects in deep and or ultra deep submicron technology due to close spacing of buses crosstalk, crosstalk delay, and signal integrity & transient malfunctions are projected to present critical challenges. In order to protect the On-chip interconnect infrastructures against these transient malfunctions and or to modify the data inputs single error correction and multiple error correction type joint crosstalk avoidance with double error correcting and simultaneous quadruple error detecting encoding & decoding techniques are proposed. These not only make the on-chip interconnect architecture tolerant against transient malfunctions, but also lower power dissipation.