CMOS Active Pixel Sensor (APS) Imager for Scientific Applications (original) (raw)
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IEEE Transactions on Electron Devices, 2000
For the Extreme Ultraviolet Imager (EUI) of the Solar Orbiter mission, to be launched in 2017, complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) prototypes have been developed with several test pixel designs. A set of measurements was carried out to evaluate their performance characteristics in visible and in EUV wavelengths. We present the results of measurement campaigns that lead to the selection of a preferred pixel design in regard to the scientific performance requirements of the EUI Flight Model detectors, i.e. back-thinned CMOS APS devices of 2048 x 2048 and 3072 x 3072 pixels formats with a 10 µm pixel pitch.
CMOS-APS Detectors for Astrophysical Applications
Since three years, we have started, a research program to select a suitable detector based on the Complementary Metal Oxide Semiconductor Active Pixel Sensor (CMOS-APS) technology with a sufficient sensitive area for astrophysical applications. Thanks to the CMOS technology, the pixel addressing and the readout circuits as well as the analogue-to-digital converters are integrated into the chip. This unique characteristic makes the CMOS-APS a good candidate for a very compact, low power consumption, imager system. With time the CMOS-APS performances will become very similar to those of CCDs. Here we compare the CCD and CMOS-APS technologies and explain why, for our application, a CMOS-APS is better suited than a CCD.
The dual-gain 10 µm back-thinned 3k x 3k CMOS-APS detector of the Solar Orbiter Extreme UV Imager
2014
The Extreme Ultraviolet Imager (EUI) on-board the Solar Orbiter mission will provide image sequences of the solar atmosphere at selected spectral emission lines in the extreme and vacuum ultraviolet. For the two Extreme Ultraviolet (EUV) channels of the EUI instrument, low noise and radiation tolerant detectors with low power consumption and high sensitivity in the 10-40 nm wavelength range are required to achieve the science objectives. In that frame, a dual-gain 10 µm pixel pitch back-thinned 1k x 1k Active Pixel Sensor (APS) CMOS prototype has been tested during the preliminary development phase of the instrument, to validate the pixel design, the expected EUV sensitivity and noise level, and the capability to withstand the mission radiation environment. Taking heritage of this prototype, the detector architecture has been improved and scaled up to the required 3k x 3k array. The dynamic range is increased, the readout architecture enhanced, the power consumption reduced, and the...
A 512×512 CMOS Monolithic Active Pixel Sensor with integrated ADCs for space science
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2003
In the last few years, CMOS sensors have become widely used for consumer applications, but little has been done for scientific instruments. In this paper we present the design and experimental characterisation of a Monolithic Active Pixel Sensor (MAPS) intended for a space science application. The sensor incorporates a 525  525 array of pixels on a 25 mm pitch. Each pixel contains a detector together with three transistors that are used for pixel reset, pixel selection and charge-to-voltage conversion. The detector consists of four n-well/p-substrate diodes combining optimum charge collection and low noise performance. The array readout is column-parallel with adjustable gain column amplifiers and a 10-bit single slope ADC. Data conversion takes place simultaneously for all the 525 pixels in one row. The ADC slope can be adjusted in order to give the best dynamic range for a given brightness of a scene. The digitised data are output on a 10-bit bus at 3 MHz. An on-chip state machine generates all of the control signals needed for the readout. All of the bias currents and voltages are generated on chip by a DAC that is programmable through an I 2 C compatible interface. The sensor was designed and fabricated on a standard 0.5 mm CMOS technology. The overall die size is 16.7 mm  19.9 mm including the associated readout electronics and bond pads. Preliminary test results show that the full-scale design works well, meeting the Star Tracker requirements with less than 1-bit noise, good linearity and good optical performance. r
Backside illuminated thinned CMOS image sensors for space imaging
2008 IEEE Sensors, 2008
This paper presents two aspects of ongoing research at Imec, to develop high-end CMOS APS sensors, optimized for space-born imaging. Both hybrid and monolithic thinned backside illuminated CMOS imagers with a unique combination of techniques and performance enhancing concepts have been developed. Here we report on their radiation tolerance and UV sensitivity, two critical characteristics for space science imaging instruments. Radiation testing, using both proton and gamma irradiation, of CMOS imagers proved that dark current performance did not significantly deteriorate. Also, initial test images taken under 185-400 nm illumination, showed the imagers to be UV sensitive.
Thin Film on CMOS Active Pixel Sensor for Space Applications
Sensors, 2008
A 664 x 664 element Active Pixel image Sensor (APS) with integrated analog signal processing, full frame synchronous shutter and random access for applications in star sensors is presented and discussed. A thick vertical diode array in Thin Film on CMOS (TFC) technology is explored to achieve radiation hardness and maximum fill factor.
High Energy, Optical, and Infrared Detectors for Astronomy V, 2012
The success of the next generation of instruments for 8 to 40-m class telescopes will depend upon improving the image quality (correcting the distortion caused by atmospheric turbulence) by exploiting sophisticated Adaptive Optics (AO) systems. One of the critical components of the AO systems for the E-ELT has been identified as the Laser/Natural Guide Star (LGS/NGS) WaveFront Sensing (WFS) detector. The combination of large format, 1760x1680 pixels to finely sample (84x84 sub-apertures) the wavefront and the spot elongation of laser guide stars, fast frame rate of 700 (up to 1000) frames per second, low read noise (< 3e-), and high QE (> 90%) makes the development of such a device extremely challenging. Design studies by industry concluded that a thinned and backside-illuminated CMOS Imager as the most promising technology. This paper describes the multi-phased development plan that will ensure devices are available on-time for E-ELT first-light AO systems; the different CMOS pixel architectures studied; measured results of technology demonstrators that have validated the CMOS Imager approach; the design explaining the approach of massive parallelism (70,000 ADCs) needed to achieve low noise at high pixel rates of ~3 Gpixel/s ; the 88 channel LVDS data interface; the restriction that stitching (required due to the 5x6cm size) posed on the design and the solutions found to overcome these limitations. Two generations of the CMOS Imager will be built: a pioneering quarter sized device of 880x840 pixels capable of meeting first light needs of the E-ELT called NGSD (Natural Guide Star Detector); followed by the full size device, the LGSD (Laser Guide Star Detector). Funding sources: OPTICON FP6 and FP7 from European Commission and ESO.
Realization and application of a 111 million pixel backside-illuminated detector and camera
Storage and Retrieval for Image and Video Databases, 2007
A full-wafer, 10,580 times\timestimes 10,560 pixel (95 times\timestimes 95 mm) CCD was designed and tested at Semiconductor Technology Associates (STA) with 9 um square pixels and 16 outputs. The chip was successfully fabricated in 2006 at DALSA and some performance results are presented here. This program was funded by the Office of Naval Research through a Small Business Innovation in Research (SBIR) program requested by the U.S. Naval Observatory for its next generation astrometric sky survey programs. Using Leach electronics, low read-noise output of the 111 million pixels requires 16 seconds at 0.9 MHz. Alternative electronics developed at STA allow readout at 20 MHz. Some modifications of the design to include anti-blooming features, a larger number of outputs, and use of p-channel material for space applications are discussed.
Monolithic and hybrid backside illuminated active pixel sensor arrays
Sensors, Systems, and Next-Generation Satellites XIII, 2009
Two types of backside illuminated CMOS Active Pixel Detectors--optimized for space-borne imaging--have been successfully developed: monolithic and hybrid. The monolithic device is made out of CMOS imager wafers postprocessed to enable backside illumination. The hybrid device consists of a backside thinned and illuminated diode array, hybridized on top of an unthinned CMOS read-out. Using IMEC's innovative techniques and capabilities, 2-D arrays with a pitch of 22.5 µm have been realized. Both the hybrid and well as the monolithic APS exhibit high pixel yield, high quantum efficiency (QE), and low dark current. Cross-talk can be reduced to zero in the hybrid sensors utilizing special structures: deep-isolating trenches. These trenches physically separate the pixels and curtail cross-talk. The hybrid imagers are suitable candidates for advanced "smart" sensors envisioned to be realized as multi-layer 3D integrated systems. The design of both these types of detectors, the key technology steps, the results of the radiometric characterization as well as the intended future developments will be discussed in this paper.
A Fully Depleted Backside Illuminated CMOS Imager with VGA Resolution and 15 micron Pixel Pitch
2013
Presented is the development of a monolithic backside illuminated CMOS image sensor with a resolution of 640 x 512 pixels, fabricated on high resistivity silicon. Wafers with fully processed CMOS circuitry on the front side are thinned and a backside contact is added. By applying a bias voltage of 100V to this backside contact, the up to 200 micron thick silicon membrane can be fully depleted and a quantum efficiency up to 60% at a wavelength of 1000nm be achieved. The vertical PIN photodiode is predicted to have a characteristic response time of 2.8 nsec at that thickness and bias voltage, a bulk limited dark current of 4nA/cm at room temperature and can be read out with very little noise due to its small specific capacitance of only a few aF/pixel. With the implemented charge domain 2x2 binning the signal to noise ratio increases by a factor 4, just like in CCD’s. Different from CCDs though, also the frame rate increases by a factor 4 in our CMOS sensor. The highly programmable de...