Sequential and Parallel Algorithms for the Addition of Big-Integer Numbers (original) (raw)
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Sequential & Parallel Algorithms for Big-Integer Numbers Subtraction
2012
Many emerging computer applications require the processing of large numbers, larger than what a CPU can handle. In fact, the top of the line PCs can only manipulate numbers not longer than 32 bits or 64 bits. This is due to the size of the registers and the data-path inside the CPU. As a result, performing arithmetic operations such as subtraction on big-integer numbers is to some extend limited. Different algorithms were designed in an attempt to solve this problem; they all operate on big-integer numbers by first converting them into a binary representation then performing bitwise operations on single bits. Such algorithms are of complexity O(n) where n is the total number of bits in each operand. This paper proposes two new algorithms for performing arithmetic subtraction on big-integer numbers. The two algorithms are different in that one is sequential while the other is parallel. The similarity between them is that both follow the same concept of dividing the big-integer inputs into several blocks or tokens of 60 bits (18 digits) each; thus reducing the input size n in O(n) by a factor of 60. Subtraction of corresponding tokens, one from each operand, is performed as humans perform subtraction, using a pencil and a paper in the decimal system. Both algorithms are to be implemented using MS C#.NET 2005 and tested over a multiple processor system. Further studies can be done on other arithmetic operations such as addition and multiplication.
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Proc. First Internat. Symp. Parallel …, 1994
This paper reports on an empirical study of several par-allel implementations of arbitrary precision integer mul-tiplication. To date we have investigated several parallel implementations of Karatsuba's algorithm on a network of workstations (our experiments consider up to 27 pro-cessors). ...
Approaches for the Parallelization of Software Implementation of Integer Multiplication
In this paper there are considered several approaches for the increasing performance of software implementation of integer multiplication algorithm for the 32-bit & 64-bit platforms via parallelization. The main idea of algorithm parallelization consists in delayed carry mechanism using which authors have proposed earlier. The delayed carry allows to get rid of connectivity in loop iterations for sums accumulation of products, which allows parallel execution of loops iterations in separate threads. Upon completion of sum accumulation threads, it is necessary to make corrections in final result via assimilation of carries. First approach consists in optimization of parallelization for the two execution threads and second approach is an evolution of the first approach and is oriented on three and more execution threads. Proposed approaches for parallelization allow increasing the total algorithm computational complexity, as for one execution thread, but decrease total execution time o...
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The problem of arithmetic operations performance in number fields is actively researched by many scientists, as evidenced by significant publications in this field. In this work, we offer some techniques to increase performance of software implementation of finite field multiplication algorithm, for both 32-bit and 64-bit platforms. The developed technique, called “delayed carry mechanism,” allows to preventing necessity to consider a significant bit carry at each iteration of the sum accumulation loop. This mechanism enables reducing the total number of additions and applies the modern parallelization technologies effectively.
International Journal of Scientific Research in Science and Technology, 2022
Cryptographic applications and pseudo random generator perform modular arithmetic three operand is the basic fundamental unit used in all these applications. For performing three operand additions, CSA (carry save adder) is one of the most widely used adders[5]. But in CSA in the final stage, carry is propagated which impacts the delay. Prefix parallel adders are therefore employed to get around this. The parallel prefix adders use more space even though performance in terms of latency is improved. Parallel prefix adders can also be used to build three operand adders. A brand-new, high-speed, and hardware-efficient adder technique is used to boost performance in terms of latency and area. This adder approach uses four stages to achieve three operand addition. Since Han Carlson adder is used in third stage, the suggested adder is not area efficient. To overcome this, in this paper we are replacing the Han Carlson parallel prefix adder with sklansky adder.
Performance evaluation of FPGA implementations of high-speed addition algorithms
Boston, Massachusetts, USA, 1996
Driven by the excellent properties of FPGA's and the need for high-performance and flexible computing machines, interest in FPGA-based computing machines has increased dramatically. Fixed-point adders are essential building blocks of any computing systems. In this work, various high-speed addition algorithms are implemented in FPGA's devices, and their performance is evaluated with the objective of finding and developing the most appropriate addition algorithms for implementing in FPGA's, and laying the groundwork for evaluating and constructing FPGA-based computing machines. The results demonstrate that the performance of adders built with the FPGA's dedicated carry logic combined with some other addition algorithms will be greatly improved, especially for larger adders.
Digit-Wise Parallelism of Additive Operations in Numeration Systems with Redundant Digits
2020
An introduction and the state of work of the project for the implementation of high-precision arithmetic in an overlaying numeration system, which provides digit-wise parallelism of operations of addition and subtraction of real numbers with restricted carry propagation only by 1–2 bits, is presented. The historical origins of ideas behind such numeration systems in the history of mathematics, dating back to A.L. Cauchy (1840) and L.E.J. Brouwer (1921), are outlined. We explain a simplest overlaying system referred to as "three halves". It is built on the binary system by adding a extra (redundant) third digit representing an interval overlaying with the intervals of 0 and 1. We demonstrate an addition scheme for it, which propagates a carry to next two positions. A simpler scheme with carry propagation to only one position is also shown, and we argue that it requires two redundant digits and a numeration system base not less than 3.
Design and Implementation of Fast Addition Using QSD for Signed and Unsigned Numbers
Binary Signed Digit Numbers are known to allow limited carry propagation with more complex addition process. Some of the limitations of this system are computational speed which limits formation and propagation of carry especially as the number of bits increases. Therefore it provides large complexity and low storage density. Carry free arithmetic operations can be achieved using a higher radix number system such as Quaternary Signed Digit (QSD) and it allows higher information storage density, less complexity. A high speed area effective adders and multipliers can be implemented using this technique. Carry free addition and other operations on a large number of digits such as 64, 128, or more can be implemented with constant delay and less complexity. The Design is simulated & synthesized using Modelsim6.0.
Speeding up the Multiplication Algorithm for Large Integers
2020
Multiplication is one of the basic operations that influence the performance of many computer applications such as cryptography. The main challenge of the multiplication operation is the cost of the operation as compared to other basic operations such as addition and subtraction, especially when the size of the numbers is large. In this work, we investigate the use of the window strategy for multiplying a sequence of large integers to design an efficient sequential algorithm in order to reduce the number of bit-multiplication operations involved in multiplying a sequence of large integers. In our implementation, several parameters are considered and measured for their effect on the proposed algorithm and the best-known sequential algorithm in the literature. These parameters are the size of the sequence of integers, the size of the integers, the size of the window, and the distribution of the data. The experimental results prove the effectiveness of the proposed algorithm are compar...