From energy-delay metrics to constraints on the design of digital circuits (original) (raw)
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Delay optimization considering power saving in dynamic CMOS circuits
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Performance variation is one of the primary concerns in nanometer-scale dynamic CMOS circuits. This performance variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, a Process Variation-aware Transistor (PVT) sizing algorithm is proposed, which is capable of significantly reducing worst-case delay, delay uncertainty, and delay sensitivity to process variations in dynamic CMOS circuits. The proposed algorithm is based on identifying the significance of all timing paths in the design, increasing the sizes of transistors that appear in most number of paths to reduce delays of most paths. In parallel, it minimizes the channel load by reducing the size of transistors in the interacting paths, which will lead to a power saving. Additional advantages in this algorithm include its simplicity, accuracy, independent of the transistor order, and initial sizing factors. Using 90 nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 36.9%, delay uncertainty by 44.1%, delay sensitivity by 19.8%, and power-delay-product by 35.3% when compared to their initial performances.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
Signal delay, chip area, and power dissipation are conflicting criteria for designing high performance VLSI MOS circuits. This paper describes global optimization of transistor sizes in digital CMOS logic circuits with the design tool multiobjective gate level optimization (MOGLO). Analytical models for the design objectives are presented and novel algorithms are discussed. Different techniques were combined to solve the circuit optimization problem with low computational costs. Precise gate level delay models guarantee meaningful results especially for high-speed logic circuits.
With the proliferation of mobile wireless communication and embedded systems, the energy efficiency becomes a major design constraint. The dissipated energy is often referred as the product of power dissipation and the input-output delay. Most of electronic design automation techniques focus on optimising only one of these parameters I gratefully acknowledge the support of IDA Ireland and Synopsys for the financial support of this work. Lastly to my fianc Vivek who has always been a tremendous source of encouragement, confidence and love. v
Energy–delay tradeoffs in combinational logic using gate sizing and supply voltage optimization
2002
This paper relates the potential energy savings to the energy profile of a circuit. These savings are obtained by using gate sizing and supply voltage optimization to minimize energy consumption subject to a delay constraint. The sensitivity of energy to delay is derived from a linear delay model extended to multiple supplies. The optimizations are applied to a range of examples that span typical circuit topologies including inverter chains, SRAM decoders and adders. At a delay of 20% larger than the minimum, energy savings of 40% to 70% are possible, indicating that achieving peak performance is expensive in terms of energy.
Physical macromodelling of the dynamic behaviour of CMOS VLSI circuits: Part I
Microelectronics Journal, 1992
The basic purpose of this paper is to present a physical analysis of the transient behaviour of CMOS circuits. A chain ofinverters is used as a vehicle for deriving general conclusions on the intimate physics of the switching process in CMOS digital networks. The analysis emphasizes the role of the dynamic thresholdvoltages, which define the initial instants of activity of the switching transistors and stresses the relevance of the intrinsic delay, tid, on the propagation delay time, tva, of an inverting gate. The effect of scaling down the device on the speed of response of these gates is also studied. It is shown that the continuous reduction in tpd, with smaller dimensions, is mainly due to a decrease in tid. The validity of the proposed analysis is ascertained by extensive circuit simulations.
Delay optimization of CMOS logic circuits using closed-form expressions
Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040)
CMOS remains the mainstream IC technology and optimization of digital CMOS circuits is a major focus of research. This paper presents a comprehensive model for estimation and optimization of the delay in submicron digital CMOS circuits. Our delay model for a logic gate depends on the topology of the gate, the size and topology of the preceding gate, and the load. This model is explicit in terms of the widths of the transistors and lead to closed-form formulas for optimization of digital CMOS gates. These formulas are simplified and approximated into rules of thumb for quick optimization and obtaining initial guess for running a CAD tool. Delay optimization of a critical path is performed by solving a set of non-linear transistor sizing formulas using iteration. Very good agreement is observed between the model and HSPICE simulations.
Energy consumption in VLSI circuits
Proceedings of the twentieth annual ACM symposium on Theory of computing - STOC '88, 1988
We study energy consumption in CMOS-style VLSI circuits, where a wire of length I consumes energy O(I) when switching. Three model are considered: the rrttislcWl model where a wire is assumed to switch at most once if the input changes. the n~u//i.s~~~i~& mode/ which allows ihr pctssibility of multiple switches caused by uncuntrotled dclnys, and the c./uc.k model which also lakes clock distribulion cncrgy into account. Previous lower bound rcsuI(s for 1111' uniswitch model 3pplicd only to cir'cliits whcrc intcrmc-Jiatc data \vL'i'c\ iicll L'nccdcd (for cbxamplc. in itnary) by using additional wires and arc;1 lo rcducc lhc cnsr.gy. WC show 11131 sticI1 encodings c;ln bc usct'ul for adding two tr-hit nunihers using synchronous b<,olcan circuils (cncrgy reduction from (+(n log tl) to O(tr log II/(log log w)), but not for transitivc functions such as the cyclic shift of n bits (energy G(rr2)). For the multiswitch modei;-we develop layouts that achieve energy close lo the uniswitch case for these problems. and show a separation result between the uniswitch and multiswitch models. Finally. some energy-period tradeoffs are shown for the dock model.
Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization
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Due to the increased importance of speed on microprocessor circuits, the complexity in transistor sizing for timing optimization increases due to channel-connected transistors on various paths of the design. In this paper, an efficient approach to transistor sizing of dynamic CMOS circuits for timing optimization while considering the Load Balance of Multiple Paths, named LBMP, is proposed. The iterative optimization algorithm is a deterministic approach and illustrated first by a 2-b weighted binary-to-thermometric converter (BTC), of which the critical path is optimized from an initial delay of 287.57 ps to an optimal delay of 161.37 ps which accounts for a 43.9% delay improvement. Then by a 64-b adder partitioned to a mixed dynamic-static style, the critical path is optimized to 686.11 ps and the power delay product is optimized to 91.6 pJ.
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004
This paper presents an analysis of how the power dissipation of on-chip buses is affected by introducing a relative delay between the switching lines. Relative delay is shown to reduce the dissipated power of oppositely switching lines while causing a power penalty for similarly switching lines. A new low-power bus scheme that uses this effect is proposed and analyzed. As the introduced delay increases, the achieved power reduction increases while decreasing the bus throughput. Thus, a tradeoff between power reduction and throughput is required when selecting the imposed relative delay. The proposed low-power scheme, dynamic delayed line bus (DDL) scheme, led to a power reduction of up to 25%, 33%, and 42% when applied to data, address, and differential buses, respectively. Simple DDL hardware is designed and implemented in a 0.18-m TSMC CMOS technology and applied to a 4500-m long Metal4 bus. Circuit simulation results for different bus widths are presented.