Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip (original) (raw)
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A generic wrapper architecture for multi-processor SoC cosimulation and design
Proceedings of the ninth international symposium on Hardware/software codesign - CODES '01, 2001
In communication refinement with multiple communication protocols and abstraction levels, the system specification is described by heterogeneous components in terms of communication protocols and abstraction levels. To adapt each heterogeneous component to the other part of system, we present a generic wrapper architecture that can adapt different protocols or different abstraction levels, or both. In this paper, we give a detailed explanation of applying the generic wrapper architecture to mixed-level cosimulation. As preliminary experiments, we applied it to mixed-level cosimulation of an IS-95 CDMA cellular phone system. 1 Introduction In designing embedded multi-processor SoCs (systems-on-chip), communication refinement is one of crucial tasks since the communication implementation can have significant impact on system performance in terms of runtime, area, power consumption, etc. [1][2][3]. It is also a challenging task since complex functional and communication requirements of current embedded SoCs require application-specific processors (e.g. CPU's, DSP's, IP's, etc.) and high-performance/complex communication networks (e.g. giga bytelevel communication bandwidth, multi-point master/slave communication, etc.). To ease the complexity of communication refinement, most of current system design methods adopt design reuse and usage of multiple abstraction levels of communication [4][5][6][7][8][9]. In such design methods, during communication refinement, the system specification consists of heterogeneous components in terms of communication protocols and abstraction levels. For instance, since reused components such as IP's can have their own communication protocols that have already been fixed, the system specification, where IP's are connected with each other via a common communication resource (e.g. on-chip bus), has multiple communication protocols. System refinement with multiple abstraction levels can give an intermediate system specification that consists of subsystems or components at different abstraction levels. To integrate heterogeneous components within a system, wrappers have been widely used for simulation and synthesis [4][8][9] [10][11][12][13][14]. In simulation, for instance, BFM (bus functional model) encapsulates a functional model with a cycle-accurate interface [10][11]. BCASH (bus-cycle accurate shell) adapts RPC (remote procedural call) and cycle-accurate communication [8][9]. In [13] and [14], interfaces of mixed-level cosimulation are presented between protocol-fixed communication and cycle-accurate communication [13] and protocol-neutral and protocol-fixed communication [14]. In system synthesis, a bus wrapper, a processor template, or a protocol transducer is used to adapt a communication protocol of reused component to that of on-chip bus [4][6][7]. In [12], COSY communication IP's use a set of specific wrappers depending on the combinations of HW-SW mapping. Previous approaches to the usage of wrappers have limitations in that their application is limited (1) to either of simulation (e.g. BFM, BCASH, [13], and [14]) or synthesis (e.g. on-chip bus wrapper, [15], [16]), (2) to a specific pair of abstraction levels: e.g. BFM (between functional and cycle-accurate) and BCASH (between RPC and cycle-accurate), or (3) to a set of specific wrappers [12]. Compared to them, our contribution is to present a single generic wrapper architecture that is applicable (1) to both simulation and synthesis and (2) to various combinations of abstraction levels/ communication protocols. In this paper, we present a generic wrapper architecture and explain the details of applying the architecture to mixed-abstraction-level (in short, mixed-level) cosimulation. Its application to synthesis is presented in [17]. This paper is organized as follows. In Section 2, we introduce the generic wrapper architecture. In Section 3, we present our design flow. We explain the application of generic wrapper architecture to mixed-level cosimulation in Section 4. In Section 5, we give experimental results. We conclude this paper in Section 6.
International Journal of Embedded Systems, 2005
System-on-chip (SoC) is developing as a new paradigm in electronic system design. This allows an entire hardware/software system to be built on a single chip, using predesigned components. This paper examines the achievements and future of novel approach and flow for an efficient design of application-specific multiprocessor system-on-chip (called GAM-SoC). The approach is based on a generic architecture model which is used as a template throughout the design process. The key characteristics of this model are its great modularity, flexibility and scalability which make it reusable for a large class of applications. In the flow, architectural parameters are first extracted from a high-level system specification and then used to instantiate architectural components, such as processors, memory modules, IP-hardware blocks, and on-chip communication networks. The flow includes the generation of hardware/software wrappers that adapts the processor to the onchip communication network in an application-specific way. The feasibility and effectiveness of this approach are illustrated by significant demonstration examples. Index Terms-Component-based design, generic architecture model, systematic design methodology, on-chip communication wrappers, AHB-AMBA, multiprocessor SoC. I. INTRODUCTION o accommodate the ever increasing performance requirements of application domains such as xDSL technology, networking, wireless, game applications, multiprocessor SoCs are more and more required [34]. Often, the multiprocessor SoC architectures require for applicationspecific optimization heterogeneous processors (DSP, CPUs), signal processing hardware, hardware controllers, DRAMs, Flash Memories, high-performance on-chip communication interfaces, and sophisticated communication protocols [11].
Colif: A design representation for application-specific multiprocessor SOCs
IEEE Design & Test of Computers, 2001
THE ADOPTION OF SYSTEM-ON-A-CHIP (SOC) architectures in future embedded-system designs will bring many advantages in terms of performance, cost, reliability, power consumption, and system size. However, to fully benefit from those advantages, designers must fine-tune the SOC architecture to suit application-specific characteristics and requirements. An application-specific multiprocessor SOC architecture (ASMSA) constitutes an ideal hardware platform since, in theory, it can be configured to fit the application's needs exactly. Such architectures allow many customizations. One of the most important design decisions is the topology and protocols chosen for communication between processors, memories, and peripherals. Achieving optimal ASMSA customization for complex applications is an overwhelming task because customizations are interdependent. Most researchers agree that independently refining communication and system behavior is a good strategy to reduce system design complexity and to achieve solutions that are sufficiently close to optimal. 1 This strategy leads naturally to a design flow in which the communication infrastructure and application code customizations follow independent paths during mapping of the system specification into an ASMSA. 2 The designer can perform these customizations concurrently if the design model separates communication and computation. A design representation for automating the ASMSA design flow must take these issues into account. The choices we have mentioned imply many trade-offs between design complexity, system performance, degree of automation, verification, and design reuse. A design model targeted at efficient ASMSA synthesis must support three main features: I Flexible communication modeling. The intrachip communication network must be modeled flexibly because application-specific optimizations might lead to a very complex architecture in which multiple topologies and protocols coexist. Furthermore, for flexibility's sake, communication models must not
Synthesis of Application-Specific Multiprocessor Architectures
Proceedings of the 28th ACM/IEEE Design …, 1991
This paper describes a formal technique for automated synthesis of multiprocessor systems for given applications. The application task is specified in terms of a graph, and the architecture synthesized includes a set of processing elements and the interconnection architecture between them. The technique generates a task execution schedule along with the architecture. The technique involves creation of a Mixed Integer-Linear Programming (MILP)model and solution of the model. Synthesis of a few example architectures is reported.
Unifying memory and processor wrapper architecture in multiprocessor SoC design
15th International Symposium on System Synthesis, 2002.
In this paper, we present a new methodology for application specific multiprocessor system-on-chip design. This approach facilitates the integration of existing components with the concept of wrapper. Wrappers allow automatic adaptation of physical interfaces to a communication network. We also give a generic architecture to produce these wrappers, either for processors or for other specific components such as memory IP. This approach has successfully been applied on a low-level image processing application.
Design and programming of embedded multiprocessors
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04, 2004
We present design technology for the structured design and programming of embedded multi-processor systems. It comprises a task-level interface that can be used both for developing parallel application models and as a platform interface for implementing applications on multi-processor architectures. Associated mapping technology supports refinement of application models towards implementation. By linking application development and implementation aspects, the technology integrates the specification and design phases in the MPSoC design process. Two design cases demonstrate the efficient implementation of the platform interface on different architectures. Industry-wide standardization of a task-level interface can facilitate reuse of function-specific hardware / software modules across companies.
DESIGN AND IMPLEMENTATION OF EFFICIENT BUS ARCHITECTURE FOR SYSTEM-ON-CHIP
The PEs of an MPSoC is related to the application context and requirements. Two from of families' architectures. One side, heterogeneous MPSoCs are composed of different PEs (processors, memories, accelerators and peripherals). These platforms were certainly pioneered: the C5 Network Processor, Nexperia and OMAP as shown in fig. The second family represents homogeneous MPSoCs, pioneered by the Lucent Daytona architecture where the same tile is instantiated several times. This chapter targets both 4 | P a g e
Designing an application-specific System-on-Chip (SoC)
Abstract — A system on chip is an embedded system consisting of several components present on a single chip meant for the execution of a specific task or a series of tasks. Most embedded systems consist of on chip peripherals other than the CPU, we shall therefore limit our study to multiprocessor SoCs, so as to differentiate SoCs from ordinary embedded systems. In this paper we explore some of the existing techniques for the development of SoCs for different applications. For this purpose we have studied in depth the choice of processor architecture, the communication architecture, the memory architecture as well as a brief study of the CAD design flow techniques.
Multiprocessor SoC platforms: a component-based design approach
IEEE Design & Test of Computers, 2000
SoC) design shows a clear trend toward integration of multiple processor cores. The SoC system driver section of the International Technology Roadmap for Semiconductors (http://public.itrs.net) predicts that the number of processor cores in a typical SoC will increase fourfold per technology node to match the corresponding applications' processing demands. Typical multiprocessor SoC (MPSoC) applications, such as network processors, multimedia hubs, and baseband telecommunications circuits, have particularly tight time-to-market and performance constraints that demand a very efficient design cycle. This article, derived from a paper presented at the 39th Design Automation Conference, 1 describes a component-based design automation approach for MPSoC platforms.