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Dynamic bootstrapped shift register for smart sensor arrays
Smart Materials and Structures, 2005
In this paper we demonstrate the operation of a dynamic serial-to-parallel shift register, with only four transistors per stage. A bootstrap capacitor is used to overcome the problem of transistor threshold voltage drop. We will refer to this new logic family as non-ratioed bootstrap logic (NRBL). Simulation results are presented showing the operation of the shift register along with Monte Carlo analysis to demonstrate the robustness of the circuit. A key application area for this novel shift register is in the addressing and read out of high-density smart sensor arrays.
Abstract: The choice of flip-flop technologies is an essential importance in design of VLSI integrated circuits for high speed and high performance CMOS circuits. The main objective of the papert is to design a Low-Power Pulse-Triggered flip-flop. Flip-flops are the major storage elements in all SOC’s of digital design. They accommodate most of the power that has been applied to the chip. Flip-flop is one of the most power consumption components. It is important to reduce the power dissipation in both clock distribution networks and flip-flops. The proposed low-power implicit-type P-FF design features a conditional pulse-enhancement scheme. First, the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Low power 4-bit shift registers are implemented using the proposed low power pulse triggered flip-flop with conditional pulse enhancement scheme. Keywords: IP-DCO, MHLFF,SCCER, SISO, SIPO, PIPO, PISO.
Muli-threshold low power Shift Register
2009
This journal focus on the design of the shift register in the sub-threshold region of the transistor which is called the weak inversion. In the weak inversion region of the transistor, the voltage supply is less than the threshold voltage of the transistor to minimise both of the dynamic power (while the circuit is in an active mode) and the static power (while the circuit is in the stand-by (idle) mode). The weak point of the operation of the transistor in the weak inversion region is that; the circuit operates more slowly compared to the high voltage supply design (where the transistor is in the strong inversion region). so this technique is useful for the low frequency operations mainly. We present the design and implementation of a low power Complementary Metal Oxide Semiconductor (CMOS) ten-bit shift register by using negative latch D Flip-Flop (DFF) in the sub-threshold region (weak inversion region) with relatively high speed in the active mode and low power consumption durin...
Simulation of Low-Power Shift Registers Using the MTCMOS Method with a Wide Selection of Transistors
Malaysian Journal of Science and Advanced Technology
The method of huge integrating involves implementing a significant transistor count in an extremely condensed space. Combinatorial logic has shown to be particularly effective in quantum computing as well as other designing applications. In VLSI design, the primary goal is to cut down on power consumption as well as latency. For the purpose of establishing technology and supporting the increased use of electrical machines, it is vital to decrease sub-threshold current flowing for large strains. This research explores the feasibility of implementing a shift register and without the Multi-threshold CMOS (MTCMOS) approach. At the process technology of 0.18 µm, 0.12 µm, and 90 nm, an investigation into the power loss and transmission delay characteristics of a variety of flip-flops is carried out. As technology gets shrunk, the amount of power lost through leakage rises. Using the greatest technique among all run time strategies, namely MTCMOS, helps to limit the amount of power lost du...
Self-Clocked Shift Registers Utilizing 90 nm CMOS: Design, Analysis and Insights
This paper presents an efficient approach to designing and analyzing four bit shift register utilizing self-clocked D flip-flops as integral storage components. The use of internal clock generation within these flip-flops obviates the need for external clock synchronization. These specially designed flip-flops incorporate a reduced number of transistors in comparison to conventional designs, leading to notable enhancements in power efficiency, packaging density, and operational speed. The implementation of self-triggered D flip-flops facilitates the creation of various shift register configurations, including Serial in Serial out (SISO), Serial in Parallel out (SIPO), Parallel in Serial out (PISO), and Parallel in Parallel out (PIPO). These registers not only occupy a smaller die area but also exhibit diminished power consumption and heightened operational speed when contrasted with standard counterparts. The design and simulation procedures are executed using the Microwind tool and a 90 nm CMOS technology.
Designing of Low power 4-bit Universal Shift Register
IJARSE, 2022
This research proposes a method for designing a Universal Shift Register (USR) that consumes little power. The proposed 4-bit USR is split into two sections: Control activities include right shift, left shift, and parallel loading; D flip flips need a separate register. 4*1 MUX performs these USR operations. Since flip flops play such a crucial role in USR, the PIPO shift register incorporates various types of flip flops that have undergone extensive testing and development. Finally, the suggested 4-bit USR boosted speed while using little power. A 4-bit USR is designed and validated with the help of the Xilinx 14.7 simulation tool and the Verilog HDL programming language.
Design of low power Linear feedback shift register
2014
Chip manufacturing technologies have been a key to the growth in all electronics devices over the past decades, bringing added convenience and accessibili ty through advantages in cost, size, and power consumption. Linear feedback shift register (LFSR) is key component to provide self-test of an integra ted circuit (IC). This research is implemented LFSR unt il layout level which will be a key component for l ow power application. The research explores the LFSR a s well as D flip flop using different architecture in a 0.18μm CMOS technology so that the layout area will be m ini ized as well as the power consumption will be lower. Three types of architectures are implemen ted into LFSR, which are NAND gates, pass transisto r and transmission gates. Mentor graphics tools are u sed for comparing those LFSR design in terms of CMOS layout, hardware implementation and power cons umption. The research showed that, pass transistor has smallest power consumption which is 3.1049 nano watts. M...
Advances on CMOS Shift Registers for Digital Data Storage
The shift register is the heart of the current digital data storage system. Current trends of wireless device designs are to balance the power consumption, cost and portability of the device. The worldwide research is giving emphasize on increasing the amount of memory at minimum possible space to reduce the overall size of the devices now a days. This paper reports a detailed survey on different types of shift registers in CMOS technology from the performance, design and application point of view. It also discusses the technologies available for the design of shift registers with their merits and demerits. This survey will act as a reference for the scientists to design the high-performance memory module.
Shift register is the key element to translate the parallel data to serial form or vice versa in digital circuits. It is commonly used in many applications, such as digital filters communication receivers, and image processing ASIC's. It can also a function as delay circuits and digital pulse extenders. In the existing system, the conventional N-bit unidirectional shift-register was proposed and it consists of N number of master-slave flip-flop with multiple 2-to-1 multiplexers. Also, the conventional clock signal methodology was promoted to transfer data from one stage to next stage. It occupies more silicon area and increases the power consumption of the shift register. To eradicate the above said difficulties a novel 256-bit bidirectional shift-register using BD-PLs is proposed. It simplifies the BD-PL structure by removing the contemporary signals (Qb, DR_b, and, DL_b) and also reduce the number of full swing clock signals applied to each stage. The modified method will reduce area and power consumption of the bidirectional shift register. The proposed method will be implemented using the XILINX Software technology. Index Terms-Area-efficient, bidirectional shift-register, flip-flop, pulsed clock, pulsed-latch.