Design & Development of a Large Die and Fine Pitch Wafer-Level Package for Mobile Applications (original) (raw)
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Design and development of a multi-die embedded micro wafer level package
2008
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2011
Two embedded micro-wafer-level packages (EMWLP) with 1) laterally placed and 2) vertically stacked thin dies are designed and developed. Three-dimensional stacking of thin dies is demonstrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10 mm × 10 mm × 0.4 mm and solder ball pitch of 0.4 mm. As part of the development several key processes like thin die stacking, 8-in wafer encapsulation using compression molding, low-temperature dielectric with processing temperature less than 200°C have been developed. The EMWLP components success fully pass 1000 air to air thermal cycling (-40°C to 125°C), unbiased highly accelerated stress testing (HAST) and moisture sensitivity level (MSL3) tests. Developed EMWLP also show good board level TC (>; 1000 cycles) and drop test reliability results. Integration of thin film passives like inductors and capacitors are also demonstrated on EMWLP platform. Developed thin film passives show a higher Q-factor when compared to passives on high resistivity silicon platform. Thermo-mechanical simulation studies on developed EMWLP demonstrate that systemic control over die, RDL, and package thicknesses can lead to designs with improved mechanical reliability.
Investigation of the Trace Line Failure Mechanism and Design of Flexible Wafer Level Packaging
IEEE Transactions on Advanced Packaging, 2000
In this study, a flexible wafer level packaging (FWLP) having the capability of redistributing the electrical circuit is proposed to resolve the problem of assembling a fine-pitched chip to a coarse-pitched substrate. In the FWLP, the diced chip is picked and back-sided attached to the flexible substrate after the functional testing. Besides, the solder on rubber (SOR) design is applied to expand the chip area and also to provide a buffer layer for the deformation energy from the coefficient of thermal expansion (CTE) mismatch. The design concepts as well as the fabrication processes for the fan-out type FWLP would be described herein. In our previous research, it was shown the reliability of FWLP could easily pass 1300 cycles thermal cycling test (JEDEC condition G, 40 C 125 C). Besides, the failure mode was moved from solders to copper trace lines. Therefore, the packaging level reliability of the copper trace structure of FWLP is investigated and discussed in this research. The 2 5 factorial designs with the analysis of variance (ANOVA) are conducted to obtain the sensitivity information of the packaging. Through the reliability assessment and constrained optimization technology, the fan-out FWLP could be further improved within the target range of design parameters. The FWLP structure proposed in this research can be redesigned to have the double-sided I/O capability, and will have a high potential for various advanced packaging applications. Index Terms-Coefficient of thermal expansion (CTE) mismatch, factorial analysis, fan-out, finite element method, flexible wafer level packaging (FWLP), packaging reliability, wafer level chip scale package (WLCSP). I. INTRODUCTION A S integrated circuit (IC) devices move toward small, light weight and high working frequency, the electronic packaging that applies the flip-chip design has gained in popularity. The flip-chip ball grid array type packaging provides better signal performance for high frequency applications and can reduce the resistance of the interconnect between the chip and the substrate. On the other hand, the wafer level chip scale package (WLCSP) technology completes the packaging Manuscript
Wafer-level chip-scale packaging for low-end RF products
Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004., 2004
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Embedded wafer level packages with laterally placed and vertically stacked thin dies
2009
Two embedded micro wafer level packages (EMWLP) with (1) laterally placed and (2) vertically stacked thin dies are designed and developed. 3D stacking of thin dies is illustrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10mm × 10mm × 0.4mm and solder ball pitch of 0.4mm. As part of the work several key processes like thin die stacking, 8 inch wafer encapsulation using compression molding, low temperature dielectric with processing temperature less than 200 C have been developed. The developed EMWLP components successfully pass 1000 air to air thermal cycling (-40 to 125 C), unbiased highly accelerated stress testing (HAST) and moisture sensitivity level (MSL3) tests. Developed EMWLP also show good board level TC (> 1000 cycles) and drop test reliability results. Integration of thin film passives like inductors and capacitors are also demonstrated on EMWLP platform. Developed thin film passives show a higher Q factor when compared to passives on high resistivity silicon platform. Thermo-mechanical simulation studies on developed EMWLP demonstrate that systemic control over die, RDL and package thicknesses can lead to designs with improved mechanical reliability.