A Sigma-Delta Converter with Adjustable Tradeoff between Resolution and Consumption (original) (raw)

FIRST ORDER SIGMA-DELTA MODULATOR WITH LOW-POWER CONSUMPTION IMPLEMENTED IN AMS 0.35 µM CMOS TECHNOLOGY

This paper presents a design of a switched-capacitor discrete time 1st order Delta-Sigma modulator used for a resolution of 8 bits Sigma-Delta analog to digital converter. For lower power consumption, the use of operational transconductance amplifier is necessary in order to provide wide output voltage swing and moderate DC gain. Simulation results showed that with 0.35um CMOS technology, 80 KHz signal bandwidth and oversampling rate of 64, the modulator achieved 49.25 dB Signal to Noise Ratio (SNR) and the power consumption was 5.5 mW under ±1.5V supply voltage .

Design of Low Power Discrete Time Sigma-Delta Modulator for Analog to Digital Converter

2014

Modulator is one of the most significant building-blocks in integrated discrete time component used in Sigma-Delta (ΣΔ) analog to digital converter. In this paper a novel structure of a switched-capacitor discrete time first order modulator Sigma-Delta is implemented at a supply voltage of 3 V. In addition, our design uses a Miller operational transconductance amplifier topology for low power consumption. The designed modulator has a resolution of 8 bits at a sampling frequency of 10.24 MHz. Eventually the modulator consumes only 1.16 mW of power under 3V. The core chip size of the modulator without bonding pads is 0.008 mm (76 μm x 110 μm) by using the AMS 0.35 μm CMOS technology.

First Order Sigma-Delta Modulator with Low-Power Consumption Implemented in Ams 0.35 ¬m Cmos Technology

International Journal of Research in Engineering and Technology, 2013

FIRST ORDER SIGMA-DELTA MODULATOR WITH LOW-POWER CONSUMPTION IMPLEMENTED IN AMS 0.35 µM CMOS TECHNOLOGY RADWENE LAAJIMI

Design of A high performance low-power consumption discrete time Second order Sigma-Delta modulator

Ijacsa, 2012

This paper presents the design and simulations results of a switched-capacitor discrete time Second order Sigma-Delta modulator used for a resolution of 14 bits Sigma-Delta analog to digital converter. The use of operational amplifier is necessary for low power consumption, it is designed to provide large bandwidth and moderate DC gain. With 0.35µm CMOS technology, the ΣΔ modulator achieves 86 dB dynamic range, and 85 dB signal to noise ratio (SNR) over an 80 KHz signal bandwidth with an oversampling ratio (OSR) of 88, while dissipating 9.8mW at ±1.5V supply voltage.

A 1 V second order sigma-delta modulator

ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), 1999

A second order switched capacitor sigma-delta modulator operating at a supply voltage of 1V is presented. The design relies on the elimination of critical switches by using a modified switched op-amp for the integrator and novel switched half-supply and reference voltage generators. The design has been carried out in a fully differential configuration in order to minimize errors arising from charge injection and clock-feedthrough effects. The converter has been implemented using a conventional 0.8 pm double-poly double-metal CMOS process and test results, showing more than 9 bits of resolution with oversampling ratio of 64, are presented.

Comparison of Sigma–Delta Converter Circuit Architectures in Digital Cmos Technology

Journal of Circuits, Systems and Computers, 2005

Integration of analog-to-digital signal conversion circuits into digital submicron silicon chips is required for many applications. This is typically implemented by sigma–delta circuits, which can provide good resolution without requiring trimming of component values. This paper presents an analytical comparison of noise performance in four alternative sigma–delta circuit configurations which have been presented in the literature, consisting of discrete-time and continuous-time integration in voltage-mode and in current-mode. For high resolution, superiority of switched-capacitor circuits over the alternatives is shown, based on process technology considerations. Design guidelines are outlined for selecting oversampling rate and other key parameters, in order to obtain maximal data resolution.

A 16-bit switched-capacitor sigma-delta modulator matlab model exploiting two-step quantization process

This paper presents a novel architecture of highorder single-stage sigma-delta (Σ∆) converter for sensor measurement. The two-step quantization technique was utilized to design a novel architecture of Σ∆ modulator. The time steps are interleaved to achieve resolution improvement without decreasing of conversion speed. This technique can be useful for low oversampling ratio. The novel architecture was designed to obtain high dynamic range of input signal, high signal-to-noise ratio and high reliability.

A Frequency Delta-Sigma Analog-to-Digital Converter Operating at a Power-Supply Voltage of 0.6 V

Analog Integrated Circuits and Signal Processing - ANALOG INTEGR CIRCUIT SIGNAL, 2003

This paper describes a delta-sigma analog-to-digital converter operating at a power supply voltage of 0.6V. The converter is implemented in a standard AMS 0.6 µm double poly process, and consists of afrequency-delta-sigma modulator where the transistor threshold voltage is decreased by floating-gatetechniques.

FIRST ORDER SIGMA DELTA MODULATOR USING 0.25 µM CMOS TECHNOLOGY AT 2.5 V

First order modulator is used in the sigma-delta modulator oversampled analog-to-digital (ADC) converter. Pseudo two phase latch based comparator with three stage cascading is used to get 2500 DC gain. Floating gate MOSFET is used at the input of integrator and comparator.ADC is implemented using 0.25 µm CMOS technology at 2.5 V.

A Sigma-Delta Converter with Adjustable Tradeoff between Resolution and Consumption (original) (raw)

Related papers