Implementation of a general-purpose stored-program digital optical computer (original) (raw)
Related papers
Proceedings of the IEEE, 1994
The recent demonstration of an all-optical, stored program, digital computer by our group focused on high speed optoelectronic design. It was made possible by a new digital design method known as time-of-flight design. A rudimentary, but general purpose, proof of principle computer was built, which is all-optical in the sense that all signals connecting logic gates and all memory are optical in nature. LiNbO 3 directional couplers, electro-optic switches, are used to perform logic operations In addition to demonstrating stored program operation in an optoelectronic digital computer, the system demonstrated the feasibility of the new design method, which does not use any flip flops or other bistable devices for synchronization or memory. This potentially allows system clock rates of the same order as device bandwidth. This paper describes how the time-of-flight design method was motivated by the special properties of optoelectronic digital design. The basic principles of the method we employed will be discussed along with some of its potential advantages. The experimental work with digital optical circuits leading up to and including the stored program computer experiment will then be discussed. Finally, the future potential of time-of-flight design in high bandwidth optoelectronic systems will be discussed. † The Center for Optoelectronic Computing Systems is sponsored in part by NSF grant number ECD 9015128 as part of the Engineering Research Centers Program, and the Colorado Advanced Technology Institute (CATI), an agency of the State of Colorado.
Bit-serial architecture for optical computing
Applied Optics, 1992
The design of a complete, stored-program digital optical computer is described. A fully functional, proof-of-principle prototype can be achieved by using LiNbO(3) directional couplers as logic elements and fiber-optic delay lines as memory elements. The key design issues are computation in a realm where propagation delays are much greater than logic delays and implementation of circuits without fip-flops. The techniques developed to address these issues yield architectures that do not change as their clocking speed is scaled upward and the size is scaled downward proportionally; these are called speed-scalable architectures. Signal amplitude restoration and resynchronization are accomplished by the novel technique of switching in a fresh copy of the system clock. Device characteristics that are important to the proof-of-principle demonstration are discussed, including the special properties and limitations that are important when designing with them. Design principles are exemplified by the design of an n-bit counter. Following this, the design for a stored-program bit-serial computer is described. We estimate that the described prototype architecture can be operated in the 100-MHz region with off-the-shelf components, and in the O. 1-1-THz region with foreseeable future components.
Some physical considerations on digital optical computing
1993
Since optical communication is preferable for establishing connections exceeding a certain critical length, for large system sizes the beneficial use of normally conducting wires for the shortest connections becomes an edge effect and can be ignored. This suggests that the performance and cost of an all optical computer might not be much inferior to an optimal hybrid alternative. We argue that for applications for which high bit repetition rates are useful despite large propagation delays, it might make sense to contemplate the construction of an optical digital computer.
Architectural implications of a digital optical processor
Applied Optics, 1984
A general technique is described for implementing sequential logic circuits optically. In contrast with semiconductor integrated circuitry, optical logic systems allow very flexible interconnections between gates and between subsystems. Because of this, certain processing algorithms which do not map well onto semiconductor architectures can be implemented on the optical structure. The algorithms and processor architectures which can be implemented on the optical system depend on the interconnection technique. We describe three interconnection methods and analyze their advantages and limitations.
Implementation of a fiber-optic delay-line memory
Applied Optics, 1992
The construction and operation of a 50-MHz 64 x 16 bit fiber-optic bit-serial delay-line memory is described. It consists of LiNbO 3 directional coupler switches, fused-fiber couplers, and a 4.17-km fiber loop. It is a subsystem of a bit-serial optical computer under construction by our group. We discuss delay and clock source stability requirements for the long delay line in the face of a limited phase error tolerance. The reliability testing of the memory subsystem is described. The degradation of data in the memory loop as the phase error tolerance is exceeded by a small amount is studied through the temperature dependence of the memory loop. Data are presented for the memory-loop stability with respect to temperature variations. The memory subsystem design and construction is presented. The results of these experiments support the feasibility of a 100-MHz 128 x 16 bit memory.
Optical Computing: Status and Perspectives
Nanomaterials
For many years, optics has been employed in computing, although the major focus has been and remains to be on connecting parts of computers, for communications, or more fundamentally in systems that have some optical function or element (optical pattern recognition, etc.). Optical digital computers are still evolving; however, a variety of components that can eventually lead to true optical computers, such as optical logic gates, optical switches, neural networks, and spatial light modulators have previously been developed and are discussed in this paper. High-performance off-the-shelf computers can accurately simulate and construct more complicated photonic devices and systems. These advancements have developed under unusual circumstances: photonics is an emerging tool for the next generation of computing hardware, while recent advances in digital computers have empowered the design, modeling, and creation of a new class of photonic devices and systems with unparalleled challenges....
Coder/decoder with an optical programmable logic cell
Photonic Devices and Algorithms for Computing IV, 2002
A major research area is the representation of knowledge for a given application in a compact manner such that desired information relating to this knowledge is easily recoverable. A complicated procedure may be required to recover the information from the stored representation and convert it back to usable form. Coder/decoder are the devices dedicated to that task. In this paper the capabilities that an Optical Programmable Logic Cell offers as a basic building block for coding and decoding are analyzed. We have previously published an Optically Programmable Logic Cells (OPLC), for applications as a chaotic generator or as basic element for optical computing. In optical computing previous studies these cells have been analyzed as full-adder units, being this element a basic component for the arithmetic logic structure in computing. Another application of this unit is reported in this paper. Coder and decoder are basic elements in computers, for example, in connections between processors and memory addressing. Moreover, another main application is the generation of signals for machine controlling from a certain instruction. In this paper we describe the way to obtain a coder/decoder with the OPLC and which type of applications may be the best suitable for this type of cell.
Digital optical counter using directional coupler switches
Applied …, 1991
We describe the design and implementation of a bit-serial, four-bit, binary optical counter. The counter was designed and simulated using a digital optical simulation program developed for this purpose. It consists of five switches, a 4-bit fiber loop memory to store the count, four ...
A New All-Optical Switching Node Including Virtual Memory and Synchronizer
Journal of Networks, 2010
This paper presents an architecture for an all optical switching node. The architecture is suitable for optical packet and optical burst switching and provides appropriate contention resolution schemes and QoS guarantees. A concept, called virtual memory, is developed to allow controllable and reasonable periods for delaying optical traffics. Related to its implementation, several engineering issues are discussed, including the use of loopbased optical delay lines, fiber Bragg gratings, and limited number of signal amplifications. In particular, two implementations using optical flip-flop and laser neuron network based control units are analyzed. This paper also discusses the implementation and performance of an alloptical synchronizer that is able to synchronize arriving data units to be aligned on the clock signal associated with the beginning time of slots, in the node, with an acceptable error.