Multichannel Packet Switching using SpaceWire on Regenerative Telecommunication Payload (original) (raw)

A fast packet switching satellite communication network

Ieee Infcom 91 the Conference on Computer Communications Tenth Annual Joint Comference of the Ieee Computer and Communications Societies Proceedings, 1991

A multibeam fast packet switching satellite communication network serving multiple zones is studied in this paper. The synchronous Time Division Multiple Access protocol (TDM) is use in transmitting messages in the uplink channels while the Asinchronous Time Division Multiple Access protocol (ATDM) is used in the downlink channels. Moreover, fast packet switching capabilities are assumed on-board the satellite. Alternatives for the architecture of the on-board fast packet switching fabric are considered. The perjormance of the considered approaches have been derived by theoretical analysis and computer simulations. A novel input queueing technique is also proposed and analyzed to show that it achives betterperformance with respect to the classical input queueing approach. Therefore, by means of the novel input queueing approach it is possible to lower the end-to-end delay without increasing the complexity of the on-board equipmnts. Work carried out under thefinancial suppofl of the National Research Council (C.N. R.) in the frame of the Telecommunication Project. packets attained switching while queueing is required for the other to wait for a later route.

Study and Implementation of Switching and Beam-Hopping Tchniques in Satellites with On Board Processing

2007

In this paper we address different downlink dynamic bandwidth allocation (DBA) techniques in a GEO stationary (GEO) satellite communication network. The goal is designing a low complexity system which can adapt to the terminal traffic requests. We investigate a possible way to increase the performance of the system by means of an interaction between on-board switching fabric (SF) and beam hopping (BH). We consider a system where an adaptive process provides uplink DBA, whereas a BH module works as downlink bandwidth allocator. Specifically, the BH module determines the number of carriers to be allocated to each downlink spot-beam on the basis of the traffic queues at the input of the SF. Simulation results show that the interaction between SF and BH is a good candidate to increase the performance of the system, since it allows reducing queue sizes in the satellite.

Improvements in CPU and FPGA Performance for Small Satellite SDR Applications

IEEE Transactions on Aerospace and Electronic Systems, 2017

The ongoing evolution in constellation/formation of CubeS ats along with steadily increasing number of satellites deployed in Lower Earth Orbit (LEO), demands a generic reconfigurable multimode communication platforms. As the number of satellites increase, the existing protocols combined with the trend to build one control station per CubeS at become a bottle neck for existing communication methods to support data volumes from these spacecraft at any given time. This paper explores the S oftware Defined Radio (S DR) architecture for the purposes of supporting multiple-signals from multiple-satelli tes , deploying mobile and/or distributed ground station nodes to increase the access time of the spacecraft and enabling a future S DR for Distributed S atellite S ystems (DSS). Performance results of differing software transceiver blocks and the decoding success rates are analysed for varied symbol rates over different cores to inform on bottlenecks for Field Programmable Gate Array (FPGA) acceleration. Further, an embedded system architecture is proposed based on these results favouring the ground station which supports the transition from single satellite communication to multi-satellite communications. Index Terms-Central Processing Unit (CPU), Field Programmable Gate Array (FPGA), S atellite communication, S oftware Defined Radio (S DR), S ystem-on-chip (S oC). I. INTRODUCTION MALL satellites are fast becoming a way to perform scientific and technological missions more affordably due to reduced build time, more frequent launch opportunities, larger variety of missions, more rapid expansion of the technical and/or scientific knowledge base and greater involvement of small industries/universities [1, 2]. Furthermore, there is an ongoing evolution of multiple small satellite scenarios such as FLOCK-1 [3], QB50 [4], Autonomous Assembly of a Reconfigurable Space Telescope (AAReST) [5], Surrey Training Research and Nano-Satellite Demonstrator (STRaND-2) [6] and Edison Demonstration of Smallsat Network (EDSN) [7]. The objectives of these missions are very ambitious and are driven by new complexities which require multi-mode operation of wireless transceivers [8].

A Serial High-Speed Satellite Communication CODEC: Design and Implementation of a SpaceFibre Interface

Acta Astronautica, 2020

In the last few years, satellite on-board data handling bandwidth requirements grew significantly, as well as production volume of these systems. A series of different protocols currently try to answer this need. In particular, the European Space Agency developed an open protocol solution: SpaceFibre. The SpaceFibre protocol can sustain a line rate of 6.25 Gb/s per lane (up to 16 lanes). It offers advanced and flexible Quality-of-Service features, as well as Fault Detection Isolation and Recovery services. The protocol structure has been developed so that full hardware implementation of its core layers is straightforward, granting high performances at low price in terms of complexity and power consumption, one of the most stringent requirements in space applications. In this paper, a FPGA implementation on both rad-hardened (RTAX2000, RTG4, Virtex-5) and commercial (ZYNQ 7000) devices of the SpaceFibre CODEC is presented together with its verification environment and a hardware validation setup. Particular attention is given to the trade-off between resources utilisation, power consumption and CODEC configurations, in order to enable future system adopters to efficiently explore the design space.

SpaceWire: a satellite on‐board data‐handling network

Aircraft Engineering and Aerospace Technology, 2001

SpaceWire is a network designed for handling payload data and control information on‐board a spacecraft. It provides a unified, high‐speed, data‐handling infrastructure for connecting together sensors (e.g. optical or radar instruments), processing elements (e.g. digital signal processors), mass‐memory units, downlink telemetry sub‐systems and ground support equipment (GSE). SpaceWire is intended to meet the needs of future, high‐capability space missions. It supports equipment compatibility and re‐use at both the component and sub‐system levels. This paper first considers the key factors that drove the specification of SpaceWire, explaining the particular demands imposed by the space environment. The components of a SpaceWire network are then introduced. The key features of SpaceWire are summarised and the support that SpaceWire provides for fault tolerance is described. Finally a summary is given of the current status of the SpaceWire standard and its application in space missions.

Implementation of a Dynamically Reconfigurable Processing Module for SpaceWire Networks

2010

The ESA-project "FPGA based generic module and dynamic reconfigurator" targets the development of a hardware architecture, called DRPM (for Dynamically Reconfigurable Processing Module). The goal of the DRPM is to develop a system that allows for the adaptation of hardware components in flight at run-time. This is enabled by the implementation of an SRAM-FPGA-based partially reconfigurable core, which is embedded into a system hosting a reconfiguration controller and a system controller providing suitable interfaces for space applications. Maximum flexibility is realized by implementing SpaceWire interfaces that enable the DRPM integration into a SpaceWire network. Moreover, the SpaceWire RMAP protocol is used for remote access to registers and memory banks of the DRPM.

Technical issues regarding satellite packet switching

International Journal of Satellite Communications, 1994

Many concepts for advanced communication satellite networks have recently been proposed. Critical technical issues relating to satellite packet switching for meshed very small aperture terminal networks and broadband networks are addressed. Hardware considerations, networking and testing issues are discussed.

On Board Processor and Processing Strategies for Next Generation Reconfigurable Satellite Payloads

2019 9th International Conference on Recent Advances in Space Technologies (RAST), 2019

Today, the increasing demand in higher data rates necessitates new methods as well as higher flexibility for satellite telecommunication payloads in order to address a variety of applications and customers. This paper presents one of these processing strategies that is applicable to today's processing satellite payloads aiming to meet those demands. For this purpose, a two-tier filter bank is designed as part of a digital onboard processor, which first divides the spectrum at the output of the ADC into a number of sub-bands extracting all the stacked channels in the digital domain. Following the analysis section of the first tier of operations, the extracted channels go under a secondary channelisation process to obtain much finer granularity of 31.25 kHz or 50 kHz depending on the communication standard used for data transmission. The implementation of the channeliser was delivered on a bit-true simulation model and the input and the output of the channelisers were compared and evaluated both in the time and frequency domains.

SHINe: Simulator for Satellite on-Board High-Speed Networks Featuring SpaceFibre and SpaceWire Protocols

Aerospace, 2019

The continuous innovation of satellite payloads is leading to an increasing demand of data-rate for on-board satellite networks. In particular, modern optical detectors generate and need to transfer data at more than 1 Gbps, a speed that cannot be satisfied with standardized technologies such as SpaceWire. To fill this gap, the European Space Agency (ESA) is supporting the development of a new high-speed link standard, SpaceFibre. SpaceFibre provides a data-rate higher than 6.25 Gbps, together with the possibility to use multiple Virtual Channels running over the same physical link, each one configurable with flexible Quality of Service parameters. These features make a SpaceFibre network very appealing but also complex to set up in order to achieve the desired end-to-end requirements. To help this process, a Simulator for HIgh-speed Network (SHINe) based on the open-source toolkit OMNeT++ has been developed and is presented in this paper. It supports the simulation of SpaceFibre an...

Concept for an all-digital satellite communications earth terminal

MILCOM 2009 - 2009 IEEE Military Communications Conference, 2009

Current DoD requirements call for a single Enterprise Terminal supporting up to 48/96 (threshold/objective) transmit and 56/112 (threshold/objective) receive communications carriers, not considering future expansion. The number of links supported by an Enterprise Terminal dictates aggregate servicing capacity. A single Teleport/standardized tactical entry point (STEP) site can consist of five or more terminals operating in several frequency bands. Each carrier requires individual converter and modem chains, which are linked to the antennas with a complex switch matrix subsystem. This architecture results in severe size, weight, and power (SWAP) constraints that limit expansion to support objective capacity and connectivity requirements within available facility space and infrastructure. By moving the digital conversion as close to the antenna as possible, a number of efficiencies in SWAP and performance can be achieved. The individual converters can be replaced with wideband, multi-carrier digital up and down converters co-located with the antenna. The complex switch matrix can be eliminated and replaced with a lightweight digital distribution system. The modem functions can be consolidated into a multi-card enclosure, where several carriers can be implemented on a single programmable processor card. In addition to reducing terminal complexity and SWAP, this approach also enables concepts such as hybrid mesh networks, decentralized power monitoring and control, and remote terminal control. This has the potential to dramatically increase satellite network efficiency and improve utilization of expensive satellite assets. This paper expands upon preliminary work performed to date atCERDEC.