s, 0.12mm² ADC with binary tree structure (original) (raw)

2009 IEEE Conference on Emerging Technologies & Factory Automation, 2009

Abstract

A configurable asynchronous CMOS TSMC90 nm Analogue to Digital Converter (ADC) with 4, 8 or 12-bits resolution, using a binary tree structure is presented which needs very low silicon area and relatively low power consumption for its implementation. The sampling rate of the 12-bit ADC exceeds 140MS/s and requires only 0.12 mm2 of area making it appropriate for ultra wideband

Xanthoula Birba hasn't uploaded this paper.

Let Xanthoula know you want this paper to be uploaded.

Ask for this paper to be uploaded.

Asynchronous Combo 4/8/12bit, 140MS/s, 0.12mm2 ADC with binary tree structure (original) (raw)

Asynchronous Combo 4/8/12bit, 140MS/s, 0.12mm² ADC with binary tree structure (original) (raw)