An 8-Bit Voltage Mode Analog to Digital Converter Based on Integer Division (original) (raw)

A REVIWE ARTICLE OF BASIC ADC DESIGN AND ISSUE OF OLD ALGORITHEM

Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. Wide spread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs). This has recently generated a great demand for low-power, low-voltage ADCs that can be realized in a mainstream deep-submicron CMOS technology. Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially power consumption. This paper presents a 4 bit Pipeline ADC with low power dissipation implemented in <0.18μm CMOS technology with a power supply of 1.2V

A CMOS 8-Bit High-Speed A/D Converter IC

—A novel high-speed low-power CMOS balanced comparator' circuit is proposed and implemented in an 8M fully parallel analog-to-digitaf (A/D) converter IC. A 20-MHz sampling rate with 350-mW power dissipation from a single 5-V power supply has been realized. Integral linearity of + 1/2 LSB to 8-bit conversion has heen achieved through intensive transistor dimension optimization applied to the comparator circuit, instead of employing an offset canceling tecfudque.

A Low-Power Architecture for Integrating Analog-to-Digital Converters

2020

Abstract-This paper reports on a modified architecture for single-slope integrating analog-to-digital converter (ADC) for use in image sensors and biomedical or any other applications where the value of the input analog signal has small and slow variations. In this architecture, instead of digitizing every new analog sample independently, the difference of the new sample with the previous sample is digitized. This idea will therefore considerably reduce the power consumption of the ADC. In order to illustrate the effectiveness of the proposed idea, an 8-bit, 4 kS/s ADC is designed and simulated in a 0.18μm CMOS technology. The proposed ADC is very power efficient when the input signal is very slow and has a small variation in voltage amplitude. Simulations confirm that the proposed ADC architecture shows more than 80% power saving compared to conventional architecture for an input signal amplitude of 0.2V FS .