Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs (original) (raw)
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Evaluation of triple-gate FinFETs with SiO2–HfO2–TiN gate stack under analog operation
Solid-State Electronics, 2007
This work presents the analog performance of nMOS triple-gate FinFETs with high-j dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain and improved unity gain frequency at similar channel length than halo counterparts. The FinFETs with 110 nm long channel achieve an intrinsic gain of 25 dB. Extremely large Early voltages have been measured on long channel nMOS with no halo and relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests that the devices operate in the onset of volume inversion due to the low doping level of the device body.
Nanomaterials
Multi-gate field effect transistors (FETs) such as FinFETs are severely affected by short-channel effects (SCEs) below 14 nm technology nodes, with even taller fins incurring fringing capacitances. This leads to performance degradation of the devices, which inhibits further scaling of nanoFETs, deterring the progress of semiconductor industries. Therefore, research has not kept pace with the technological requirements of the International Roadmap for Devices and Systems (IRDS). Thus, the development of newer devices with superior performances in terms of higher ON currents, acceptable leakage currents and improved SCEs is needed to enable the continuance of integrated circuit (IC) technologies. The literature has advocated integration of strained-silicon technology in existing FinFETs, which is highly effective in enhancing ON currents through the strain effect. However, the ON currents can also be amplified by intensifying the number of fins in trigate (TG) FinFETs. Thus, three-fin...
IEEE Transactions on Electron Devices, 2000
The exponential miniaturization of Si complementary metal-oxide-semiconductor technology has been a key to the electronics revolution. However, the downscaling of the gate length becomes the biggest challenge to maintain higher speed, lower power, and better electrostatic integrity for each following generation. Both industry and academia have been studying new device architectures and materials to address this challenge. In preparation for the 12-nm technology node, this paper assesses the performance of the In 0.75 Ga 0.25 As of III-V semiconductor compounds and strained-Si channel nanoscale transistors with identical dimensions. The impact of the channel material property and the device architecture on the ultimate performance of ballistic transistors is theoretically analyzed. Two-dimensional and three-dimensional real-space ballistic quantum transport models are employed with band structure nonparabolicity. The simulation results indicate three conclusions: 1) the In 0.75 Ga 0.25 As FETs do not outperform strained-Si FETs; 2) triple-gate Fin-shaped Field Effect Transistor (FinFET) surely represent the best architecture for sub-15-nm gate contacts, independently from the material choice; and 3) the simulations results further show that the overall device performance is very strongly influenced by the source and drain resistances.
2010
Distinction between triple gate (TG) and double gate (DG) silicon-on-insulator (SOI) FinFETs is presented here on the basis of their electrostatic and transport characteristics. A study missing in previous works on DG and TG FinFETs is the characterization of these structures with respect to the variation of top oxide thickness. In fact an exact value of the top-oxide thickness that can differentiate DG FinFETs from TG ones has not been reported yet. From this perspective, electrostatic and transport characteristics of DG and TG FinFETs having sub-10 nm fin dimensions are investigated in this work as a function of the top oxide thickness. To duly incorporate the quantummechanical (QM) effects in such nanoscale regime of operation, the devices are simulated by self-consistently solving the coupled Schrödinger's and Poisson's equations. Simulation results suggest that DG and TG FinFETs can be differentiated by a parameter which we define in our work with respect to the surface potentials existing beneath the top and side gates. This finding in effect proposes a critical top oxide thickness of FinFET that can draw the distinction between its DG and TG variants. The results also indicate that deposition of top oxide layer beyond a limit does not bring about any significant change in the electrostatic and transport characteristic of DG FinFETs in the ballistic limit.
Impact of gate oxide complex band structure on n-channel III–V FinFETs
2015
FinFET geometries have been developed for the sub-22 nm regime to extend Si-CMOS scaling via improved electrostatics compared to planar technology. Moreover, engineers have incorporated high-k oxide gate stacks. Beyond leakage current, less discussed is the impact of the gate oxide's complex band structure on the device performance. However, it defines the boundary condition for the channel wavefunction at the interface, which, in turn, affects the quantum confinement energy for channel electrons. Here we show that the ON-state performance of n-channel FinFETs may be sensitive to the oxide's complex band structure, especially with light-mass III-V channel materials, such as In0.53Ga0.47As. We study this effect using an ensemble semi-classical Monte Carlo device simulator with advanced quantum corrections for degeneracy and confinement effects. Our simulations suggest that using a surface oxide with a heavy effective mass may lower the channel carrier confinement energies, mitigating unwanted quantum side-effects that hinder device performance. Ultimately, future high-k stacks may benefit from oxide gate stack heterostructures balancing effective mass and dielectric permittivity considerations.
Applied Physics Letters, 2011
The variation of electrostatic and transport characteristics of silicon-on-insulator fin field effect transistors (FinFETs) having sub-10 nm fin dimensions is investigated with the variation of top oxide thickness. Capacitance voltage and ballistic transport characteristics of double gate (DG) and triple gate (TG) FinFETs are obtained by self-consistently solving the coupled Schrödinger's and Poisson's equations. Performance enhancement can be obtained in terms of both on-state current and inversion capacitance by increasing the top oxide thickness of highly scaled FinFETs. The work suggests limiting values of the device parameter to differentiate the DG and TG variants of FinFET.
Solid-State Electronics, 2016
This paper presents an experimental analysis of the analog application figures of merit: the intrinsic voltage gain (A V) and unit gain frequency, focusing on the performance comparison between silicon triple gate pFinFET devices, which were processed on both Si and Silicon-On-Insulator (SOI) substrates. The high temperature (from 25°C to 150°C) influence and different channel lengths and fin widths were also taken into account. While the temperature impact on the intrinsic voltage gain (A V) is limited, the unit gain frequency was strongly affected due to the carrier mobility degradation at higher temperatures, for both p-and n-type FinFET structures. In addition, the pFinFETs showed slightly larger A V values compared to the n-type counterparts, whereby the bulk FinFETs presented a higher dispersion than the SOI FinFETs.
Journal of Nano- and Electronic Physics, 2016
In this paper, we present the results of a 3D-numerical simulation of SOI TRI-GATE FinFET transistor. 3D-device structure, based on technology SOI (Silicon-On-Insulator) is described and simulated by using SILVACO TCAD tools and we compare the electrical characteristics results for Titanium Nitride (TiN) fabricated on Al2O3 (k ~ 9), HfO2 (k ~ 20) and La2O3 (k ~ 30) gate dielectric. Excellent dielectric properties such as high-k constant, low leakage current, threshold voltage and electrical characteristics were demonstrated. The implementation of high-k gate dielectrics is one of several strategies developed to allow further miniaturization of microelectronic components. From the simulation result; it was shown that HfO2 is the best dielectric material with metal gate TiN, which giving better subthreshold swing (SS), drain-induced barrier lowing (DIBL), leakage current Ioff and Ion/Ioff ratio.