Overview of recent direct wafer bonding advances and applications (original) (raw)

2010, Advances in Natural Sciences: Nanoscience and Nanotechnology

Direct wafer bonding processes are being increasingly used to achieve innovative stacking structures. Many of them have already been implemented in industrial applications. This article looks at direct bonding mechanisms, processes developed recently and trends. Homogeneous and heterogeneous bonded structures have been successfully achieved with various materials. Active, insulating or conductive materials have been widely investigated. This article gives an overview of Si and SiO 2 direct wafer bonding processes and mechanisms, silicon-on-insulator type bonding, diverse material stacking and the transfer of devices. Direct bonding clearly enables the emergence and development of new applications, such as for microelectronics, microtechnologies, sensors, MEMs, optical devices, biotechnologies and 3D integration.

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A study of multi-stack silicon-direct wafer bonding for MEMS manufacturing

Technical Digest. MEMS 2002 IEEE International Conference. Fifteenth IEEE International Conference on Micro Electro Mechanical Systems (Cat. No.02CH37266), 2002

Multi-stack wafer bonding is one of the most promising fabrication techniques for creating three-dimensional (3D) microstructures. However, there are several bonding issues that have to be faced and overcome to build multilayered structures successfully. Among these are:

Multi-stack silicon-direct wafer bonding for 3D MEMS manufacturing

Sensors and Actuators A: Physical, 2003

Multi-stack wafer bonding is one of the most promising fabrication techniques for creating three-dimensional (3D) microstructures. However, there are several bonding issues that have to be faced and overcome to build multilayered structures successfully. Among these are:

Low temperature silicon wafer bonding for MEMS applications

2002

Abstract This paper reports the investigation of low-temperature silicon wafer fusion bonding for MEMS applications. A bonding process utilizing annealing temperatures between 400 C and 1100 C was characterized. The silicon-silicon bonded interface was analyzed by Infrared Transmission (IT) and Transmission Electron Microscopy (TEM) and the bond strength was quantified by a four-point bending-delamination technique

Combined process for wafer direct bonding by means of the surface activation method

2004

A sequential plasma activation process consisting of oxygen reactive ion etching (RIE) plasma and nitrogen radical activation is proposed for wafer direct bonding at room temperature. The Si wafer surface is activated by oxygen RIE plasma and subsequently exposed to nitrogen radicals. The activated wafers by the two-step process were brought into contact in air followed by keeping them in air for 24 h. The wafers were bonded throughout the whole area and the bonding strength of the interface is as strong as bulk Si without any post-annealing process and wet chemical cleaning steps. XPS study indicates that the silicon surface has thermodynamically unstable characteristics. IR transmission images reveal a considerable amount of water is absorbed in the wafer surfaces during exposure to air after the plasma activation process. The high bonding strength is thought to be due to a diffusion of absorbed water into the wafer surface and a reaction between silicon oxynitride layers on the opposing wafer. TEM images show that an intermediate amorphous layer with thickness of 15 nm is formed across the interface. The bonding is so intimate that no micro-voids are found at the bonding interface. Furthermore, strong bonding of crystalline quartz and fused quartz at room temperature was also obtained by the sequential activation process.

Role of surface morphology in wafer bonding

Journal of Applied Physics, 1991

The strain patterns detected by x-ray topography in wafers bonded for silicon-on-insulator (SOI) technology were found related to the flatness nonuniformity of the original wafers. Local stresses due to the bonding process are estimated to be about 1 X 10 8 dynes/ cm 2. The stress is reduced about 100 times for the thin (0.5 µm) SOI films. Most of the wafer deformation occurs during room temperature mating of the wafers. The deformation is purely elastic even at 1200 °C. The magnitude of the stress appears insignificant for complimentary metal-oxide-semiconductor devices performance.

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