PARASITICS ACCOMMODATION IN THE CLASS-E POWER AMPLIFIER DESIGN (original) (raw)
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Analytical Design Equations for Class-E Power Amplifiers
IEEE Transactions on Circuits and Systems I-regular Papers, 2007
Many critical design trade-offs of the Class-E power amplifier (e.g power efficiency) are influenced by the switch onresistance and the value of dc-feed drain inductance. In literature, the time-domain mathematical analyses of the Class-E power amplifier with finite dc-feed inductance assume zero switch onresistance in order to alleviate the mathematical difficulties; resulting in non-optimum designs.
Design Equations for Class-E Power Amplifiers
Journal of Materials Processing Technology, 2006
In literature, it is widely accepted that the design of Class-E Power Amplifier (PA) with finite dc feed inductance requires a long iterative solution procedure. To avoid such iterative solution methods, analytical design equations should be known. The problem associated with the finite dc feed inductance Class-E PA is usually ascribed to the fact that the circuit element values are transcendental functions of the input parameters which is assumed to prevent the derivation of exact or fully analytical design equations.
Generalized Design Equations for Class-E Power Amplifiers with Finite DC Feed Inductance
IEEE Transactions on Pattern Analysis and Machine Intelligence, 2006
In literature, it is widely accepted that the design of Class-E Power Amplifier (PA) with finite dc feed inductance requires a long iterative solution procedure. To avoid such iterative solution methods, analytical design equations should be known. The problem associated with the finite dc feed inductance Class-E PA is usually ascribed to the fact that the circuit element values are transcendental functions of the input parameters which is assumed to prevent the derivation of exact or fully analytical design equations.
IET Circuits, Devices & Systems, 2016
In this study, design theory and analysis for the class E power amplifier (PA), considering the metal oxide semiconductor field effect transistor (MOSFET) parasitic input and output capacitances, are proposed. The input resistance and capacitances cause non-ideal input voltage at gate terminal, which affect the specifications of the class E PA. In the proposed study, non-linear drain-to-source, linear gate-to-drain and linear gate-to-source MOSFET parasitic capacitances are considered, while zero voltage and zero derivative switching conditions are achieved. Moreover, the input resistance and the value of the input voltage are taken into account in the design theory. According to the obtained results, the duty cycle of the MOSFET depends on the MOSFET threshold voltage, input voltage, input series resistance, and some other parameters, which will be explained in this study. A design example is finally given to describe the design procedure at 1 MHz operating frequency along with the experimental result. The circuit simulation is also performed using PSpice software. The measured results showed quantitative agreements with simulation and theory results.
Investigation on technological aspects of class E RF power amplifiers for umts applications
This paper presents results of investigation on the effects of technology on the performance of the class E power amplifier circuit. A typical class E circuit has been designed and simulated, for a typical UMTS Tx frequency (1.95 GHz) and output power ( 27dBm). Three different technologies have been used (silicon BJT, CMOS and GaAs HBT) and several important parameters (output efficiency, power added efficiency, stress put on the device) have been monitored and put in table form for comparison. Care has been taken to adapt the design in such a way to provide a maximum performance with each technology, for a fair comparison. The results are then analyzed and different tradeoffs are discussed. Possibilities for the linearization of the amplifier are considered.
Analysis and Design a 2.5 GHz Class-E Power Amplifier in Two Configurations
There are two circuit configurations that commonly used for Class-E power amplifiers, the Infinite DC-feed or Shunt capacitor configuration and the Finite DC-feed or Shunt inductor. Albeit these circuit configurations are not essentially different, however they show different behavior and performance. In this paper we have compared these Class-E configurations at 2.5 GHz. For this purpose, we have designed two class-E circuits, one with Infinite DC-feed configuration and the other with Shunt inductor configuration. We have used the GaN High Electron Mobility Transistor (HEMT) in both designs. Optimized simulations showed 69% drain efficiency, 64% PAE, and 21.46 dBm load power, in the case of Infinite DC-feed design and 71% efficiency, 64.5% PAE, and 15.93 dBm load power in the case of Shunt inductor design. It is obvious that we should consider the importance of PAE inhigh power circuits and the importance of DE in low power circuits. The results propose that Infinite DC-feed design...
A CMOS LOW VOLTAGE CLASS-E POWER AMPLIFIER FOR UMTS
In this paper we design a low-voltage class-E power amplifier (PA) in a standard CMOS 0.35µm integrated technology, to be used in a UMTS transceiver having the following specifications: f=1.95 GHz, V DC =1 V, P out =0.5 W. The designed class-E network accommodates the simultaneous presence of a parasitic ground inductance and losses in the switch and shunt-capacitor. The transistor is dimensioned for an optimum PAE (power added efficiency). Finally, we simulate the power control capabilities and highlight linearization methods.
1 a Cmos Low Voltage Class-E Power Amplifier for Umts
2015
Abstract: In this paper we design a low-voltage class-E power amplifier (PA) in a standard CMOS 0.35µm integrated technology, to be used in a UMTS transceiver having the following specifications: f=1.95 GHz, VDC=1 V, Pout=0.5 W. The designed class-E network accommodates the simultaneous presence of a parasitic ground in-ductance and losses in the switch and shunt-capacitor. The transistor is dimensioned for an optimum PAE (power added efficiency). Finally, we simulate the power con-trol capabilities and highlight linearization methods.
Optimization of Class E Power Amplifier Design above Theoretical Maximum Frequency
2008
In this contribution, the analysis on high frequency Class E design approach is presented. Starting from the classical theory, a numerical analysis is performed to extend class E feasibility at higher frequencies. The design of hybrid Class-E amplifier in LDMOS technology for UMTS base-station applications will be presented, in order to validate the theoretical results. The simulated PA reaches an output power of 40.7dBm in correspondence of 56% drain efficiency.