PARASITICS ACCOMMODATION IN THE CLASS-E POWER AMPLIFIER DESIGN (original) (raw)
This paper presents a class-E power amplifier (PA) new design algorithm optimized for monolithic implementation. This algorithm accommodates simultane- ously the parasitic ground inductance, the switch on-resistance, and the shunt ca- pacitor finite Q-factor value offering an exact solution. For total power dissipation calculation, the effects of the finite turn-off time are also considered. A class-E PA (targeted specifications correspond to a UMTS transceiver, f=1.95 GHz, Pout=0.5 W) was designed following the algorithm proposed in this paper. The simulation results fit well the theoretical solution.
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