Metal-bonded, hermetic 0-level package for MEMS (original) (raw)

2010, 2010 12th Electronics Packaging Technology Conference

This paper presents a zero-level packaging technology for hermetic encapsulation of MEMS. The technology relies on the "chip capping" of the MEMS using a metallic bond made by means of diffusion soldering of a Cu-Sn system at a temperature of around 250°C. For this, on a "capping wafer" a sealing ring (or bond frame), composed of a double layer of Cu/Sn, is grown, and on the MEMS wafer a matching ring of a single Cu layer is made. Next, the "capping chip" is assembled onto the "MEMS die", either in a die-to-wafer (D2W) or a wafer-to-wafer (W2W) fashion. The thicknesses of the layers (Cu/Sn and Cu) and the bonding process parameters (temperature and force profile) have been optimized so as to achieve a strong, hermetic package, that remains stable up to temperatures as high as ~415°C. Leak testing, based on the "membrane deflection method", revealed that the packages are air tight and He leak tight. No noticeable change of the deflection of the cap (thinned down to 20-50 μm) was observed as a result of pressurizing the packages for 11 days under He at 30 MPa.

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Wafer-level SLID bonding for MEMS encapsulation

Advances in Manufacturing, 2013

Hermetic packaging is often an essential requirement to enable proper functionality throughout the device's lifetime and ensure the optimal performance of a micro electronic mechanical system (MEMS) device. Solid-liquid interdiffusion (SLID) bonding is a novel and attractive way to encapsulate MEMS devices at a wafer level. SLID bonding utilizes a low-melting-point metal to reduce the bonding process temperature; and metallic seal rings take out less of the valuable surface area and have a lower gas permeability compared to polymer or glassbased sealing materials. In addition, ductile metals can adopt mechanical and thermo-mechanical stresses during their service lifetime, which improves their reliability. In this study, the principles of Au-Sn and Cu-Sn SLID bonding are presented, which are meant to be used for wafer-level hermetic sealing of MEMS resonators. Seal rings in 15.24 cm silicon wafers were bonded at a width of 60 lm, electroplated, and used with Au-Sn and Cu-Sn layer structures. The wafer bonding temperature varied between 300°C and 350°C, and the bonding force was 3.5 kN under the ambient pressure, that is, it was less than 0.1 Pa. A shear test was used to compare the mechanical properties of the interconnections between both material systems. In addition, important factors pertaining to bond ring design are discussed according to their effects on the failure mechanisms. The results show that the design of metal structures can significantly affect the reliability of bond rings.

Hermetically sealed on-chip packaging of MEMS devices

2000

While packaging technology of conventional integrated circuits has already become more and more complex, packaging of MEMS sensors is particularly challenging. MEMS require a higher level of dedication given the fragility of the devices and the frequent need of a controlled atmosphere (e.g. gas mixture, overpressure or vacuum) in order to achieve the proper functionality of the devices. The actions taken to meet the desired specifications typically result in large, complicated and costly packages. The hermiticity of the package over the full life-time of the MEMS device is one of the largest challenges because of a large number of vacuum feedthroughs. Using the so-called indent-reflow sealing process, we have been able to demonstrate a hermetically-sealed on-chip vacuum package. As a result, a standard global package can be used.

Challenges in the packaging of MEMS

Proceedings International Symposium on Advanced Packaging Materials. Processes, Properties and Interfaces (IEEE Cat. No.99TH8405)

The packaging of Micro-Electro-Mechanical Systems (MEMS) is a field of great importance to anyone using or manufacturing sensors, consumer products, or military applications. Currently much work has been done in the design and fabrication of MEMS devices but insufficient research and few publications have been completed on the packaging of these devices. This is despite the fact that packaging is a very large percentage of the total cost of MEMS devices. The main difference between IC packaging and MEMS packaging is that MEMS packaging is almost always application specific and greatly affected by its envirotient and packaging techniques such as die handling, die attach processes, and lid sealing. Many of these aspects are directly related to the materials used in the packaging processes. MEMS devices that are functional in wafer form can be rendered inoperable after packaging. MEMS dies must be handled only from the chip sides so features on the top surface are not damaged. This eliminates most current die pick-and-place fixtures. Die attach materials are key to MEMS packaging. Using hard die attach solders can create high stresses in the MEMS devices, which can affect their operation greatly. Lowstress epoxies can be high-outgassing, which can also affect device performance. Also, a low modulus die attach can allow the die to move during ultrasonic wirebonding resulting to low wirebond strength. Another source of residual stress is the lid sealing process. Most MEMS based sensors and devices require a hermetically sealed package. This can be done by pm~el seam welding the package lid, but at the cost of further induced stress on the die. Another issue of MEMS packaging is the media compatibility of the packaged device. MEMS unlike ICS often interface with their environment, which could be high pressure or corrosive. The main conclusion we can DISCLAIMER Portions of this document may be illegible in electronic image products. Images are produced from the best available original document. , , draw about MEMS packaging is that the package affects the performance and reliability of the MEMS devices. There is a gross lack of understanding between the package materials, induced stress, and the device performance. The material properties of these packaging materials are not well defined or understood. Modeling of these materials and processes is far from maturity. Current post-package yields are too low for commercial feasibility, and consumer operating environment reliability and compatibility are often difficult to simulate. With fu~her understanding of the materials properties and behavior of the packaging materials, MEMS applications can be fully realized and integrated into countless commercial and military applications.

Low-temperature hermetic thermo-compression bonding using electroplated copper sealing frame planarized by fly-cutting for wafer-level MEMS packaging

Sensors and Actuators A: Physical, 2018

Hermetic packaging plays an important role for optimizing the functionality and reliability of a wide variety of micro-electro-mechanical systems (MEMS). In this paper, we propose a low-temperature wafer-level hermetic packaging method based on the thermo-compression bonding process using an electroplated Cu sealing frame planarized by a single-point diamond mechanical fly-cutting. This technology has an inherent possibility of hermetic sealing and electrical contact as well as a capability of integration of micro-structured wafers. Hermetic sealing can be realized with the sealing frame as narrow as 30 m at a temperature as low as 250 • C. At such a low bonding temperature, a less amount of gases is desorbed, resulting in a sealed cavity pressure lower than 100 Pa. The leak rate into the packages is estimated by a long-term sealed cavity pressure measurement for 7 months to be less than 1.67 × 10 −15 Pa m 3 s −1. In addition, the bonding shear strength is also evaluated to be higher than 100 MPa.

Zero-level packaging for (RF-)MEMS implementing TSVs and metal bonding

2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 2011

This paper presents a 0-level packaging technology for (RF-)MEMS implementing vertical feedthroughs or through-Si-via's (TSVs) and metal bonding. A thinned capping substrate (100µm thick) equipped with Cu-coated TSVs is bonded to a MEMS substrate. The vertical feedthroughs lead to a smaller footprint and make the package ready for 3D integration. The CuSn/Cu metal bonding provides a hermetic seal for the package. A full fabrication process for thinned Caps with "chamfered" shaped TSVs (70-120µm diameter) has been developed. Highly yielding TSVs (close to 100%) displaying a resistance of a single via of less than 10m have been obtained. The performance of traversing transmission lines (CPWs) patterned on the MEMS wafer (implemented in 1µm thick Cu and connected with the external terminals via the microbumps and the TSVs) has been measured. FEM based thermo-mechanical modelling is applied in order to evaluate the critical stress points and to estimate the Cap-to-MEMS die deflection under an external pressures.

Wafer-level thin-film encapsulation for MEMS

Microelectronic Engineering, 2009

The diversity and complexity of many microelectromechanical systems (MEMS), combined with the mechanical nature of the devices involved, means that the handling, dicing and packaging of these structures can pose many problems. So-called 'zero-level' packaging options are now often used to protect the devices at the wafer scale before the wafer is diced and sent for conventional packaging. This paper describes a novel process flow for the fabrication of integrated MEMS thin-film packages within a lowtemperature, CMOS-compatible process. A double sacrificial layer is used, which encapsulates the device of interest within a shell of silicon oxide. The sacrificial layer is then removed through lateral etch channels and the shell is sealed. The technique requires minimal extra wafer space, allows the use of low-temperature materials within the process flow, and the novel channel design means that the shell may be easily sealed. Preliminary visual and electromechanical tests using simple fixed-fixed beam test structures indicate that the package is sealed, the device is undamaged and that encapsulation has little or no effect on device performance.

Self-aligned 0-level sealing of MEMS devices by a two layer thin film reflow process

Microsystem Technologies, 2004

Many micro electromechanical systems (MEMS) require a vacuum or controlled atmosphere encapsulation in order to ensure either a good performance or an acceptable lifetime of operation. Two approaches for wafer-scale zero-level packaging exist. The most popular approach is based on wafer bonding. Alternatively, encapsulation can be done by the fabrication and sealing of perforated surface micromachined membranes.

Temporary 0-Level MEMS Packaging Using a Heat Decomposable Sealing Ring

2011

This paper reports on a novel temporary 0-level packaging process for MEMS (Micro Electro Mechanical Systems), in particular MEMS for optical applications. In this process protective caps, with a heat decomposable and photopatternable polymer sealing ring, are placed by flip-chip on the MEMS wafer. The resulting temporary packages are gross leak tight, fulfil the MIL spec for shear testing and respect the thermal budget of Al-coated SiGe micro-mirrors. After debonding the cap, the SiGe mirrors are unharmed.

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