A low power thyristor-based CMOS programmable delay element (original) (raw)

Properties and Design of CMOS Thyristor Delay Elements

Journal of Integrated Circuits and Systems

The CMOS thyristor delay element and its basic operation are presented in this paper. Six variations of the thyristor design developed over the years to extend the delay length, to improve the consistency of the delay, or to control the sensitivities of the delay are also discussed. This includes the complementary thyristor, the thyristor without the current source, the thyristor with threshold elevation, the thyristor with opposing current source, the single-ended thyristor, and the thyristor-type feedback delay element. Design considerations common to all CMOS thyristors are also discussed to provide insights on topology selection, capacitive loading, and transistor sizing.

Design of a Novel Current Balanced Voltage Controlled Delay Element

International Journal of VLSI Design & Communication Systems, 2014

This paper presents a design of fast voltage controlled delay element based on modified version of low noise Current Balanced Logic (CBL). This delay element provides identical rising and falling edge delays controlled by the single control voltage. The post layout tunable delay range is from 140 ps to 800 ps over control voltage range of 0 to 2.1 V. An analysis for the delay element is also presented, which is in agreement with the simulated delays. A Delay Lock Loop (DLL) is designed using this delay element to verify its performance.

A Linear Comparator-Based Fully Digital Delay Element

2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A linear delay element is proposed in 0.18 µm CMOS technology with a power supply of 1.8V. The proposed delay element maintains linearity over a relatively large input voltage range of 1.2V and its delay range (sensitivity) can be tuned through a bias voltage. Its power dissipation is 50μW at a clock frequency of 1GHz and its robustness in different process corners has been shown through simulations. Additionally, a 6bit 107MS/s Fully Digital ADC with 1.2 V input range has been implemented using the proposed delay element. The simplicity of design and functioning of the proposed delay element contributes to its improved power and energy consumption.

A highly-linear modified pseudo-differential current starved delay element with wide tuning range

2011

This paper describes an efficient structure of a pseudo-differential current starved delay element that is used in a four stages delay line targeted for analog/mixed Delay- Locked-Loops. The designed circuit has been simulated in ADS software, using TSMC 0.18 um CMOS process at 1.5V supply voltage. Body feed technique is used to widen applicable range of control voltage. The linearity

A Digitally Controlled Shunt Capacitor CMOS Delay Line

Analog Integrated Circuits and Signal Processing, 1999

Delay-controlled CMOS delay lines have been proved useful in a number of applications, notably the digitization of short time intervals. This paper introduces a new kind of CMOS delay line, in which the delay element is an array of capacitors controlled by a digital signal vector. This choice allows for a robust implementation of the circuitry controlling the delay generation, while the maximum speed attainable by the line is high compared to the maximum speed achieved by other delay line architectures. The delay line presented here was designed to produce an accurately tunable 16 × 0.5ns delay under large temperature, supply voltage, and technological process quality variations.

Effect of changes in supply voltage on power consumption of digital CMOS delay lines

IJEER, 2016

In the beginning of the last decade, battery-powered hand-held devices such as mobile phones and laptop computers emerged. For that application we have to design a device which will consume minimum amount of energy. For that reason in this article we focused on power consumption and how to calculate the power. In this paper, an analysis of different delay lines based on CMOS architecture has been done. The effect of supply voltage on digital delay lines has been analysed as how supply voltage affected the value of power consumption of the digital delay line. After the analysis of those performance parameters, the trade-off has been made for better performance of delay lines.

In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations

IEEE Journal of Solid-State Circuits, 2000

A method is proposed to compensate for local delay variations by adjusting the supply voltage of individual circuit blocks. In-situ characterization of sub-blocks allows for voltage adjustment with minimum safety margin. Different strategies and circuit techniques for in-situ delay characterization of sub-blocks are described and compared. A dual V DD power switch scheme is proposed for discrete voltage assignment to individual sub-blocks. Experimental results are presented for a test module based on an ARM9 core, fabricated in 130-nm CMOS. Yield improvement and power reduction capabilities are demonstrated by Monte Carlo simulations. For a typical setting, a reduction of 10% in power can be achieved with the proposed dual V DD power switch concept. Using more than two supply voltages is shown to produce only small additional power savings at the price of high area overhead. The effect of the proposed scheme increases with increasing intra-die variability, which makes it suitable especially for future technologies. Index Terms-Adaptive supply voltage (ASV), crystal ball flip-flop, dynamic voltage scaling (DVS), error detection and correction, in-situ characterization, local supply voltage assignment, Razor flip-flop.

RECENT TRENDS OF POWER DELAY FOR LOW POWER & HIGH SPEED VLSI CIRCUITS

This paper, introduces an idea of the power improvement hypothesis approach, the estimation systems and streamlining circuits utilized for low power VLSI circuits. In more up to date advancements, power is an essential plan requirement. Control dissemination has soar because of transistor scaling, chip transistor tallies and clock frequencies. Effective chip configuration requires low power thought, and assurance of the areas (spots) on the pass on where control dissemination happens. The requirement for low power configuration is additionally turning into a noteworthy issue in superior computerized framework, for example, chip and advanced incorporated circuits. The approach which we use for low power circuits traverses a wide range from gadget or process level to calculation level. Keywords- optimization, VLSI, switching power, short circuit, leakagepower, voltagescaling, subthresholdleakage,

Pulse controlled memristor-based delay element

2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017

Computing circuits suffer from the process, voltage and temperature variations and aging. These factors reduce yield and lifetime of the circuits and therefore limit the advance in modern computing technology. The process variations and aging result in timing failures that often can be resolved by delay matching. However, this strategy requires delay elements which cause additional power cost. We propose an alternative approach to implementing a pulse controlled delay element using a novel "memristor" device. The delay element has three modes of operation: tune up, tune down and normal. The main advantage of this approach is the energy efficiency due to the absence of the current path in the normal mode. Furthermore, as memristor is a non-volatile device, the proposed delay element does not need to be re-initialized every time the system starts. Thus, it can save startup power and time, which is also critical in the beyond CMOS computing. We also identify and propose a solution to the backward tuning problem which occurs when the amplitude of the normal signal is higher than the memristor threshold. A prototype was built based on ferroelectric parameter set with VTEAM model and the high voltage AMS 0.35µm technology. The simulation results showed an effective delay range from 5.48ns to 13.54ns in 6 steps with the minimum tuning pulse width of 3ns and the average delay of 1.34ns per step.

Synthesizable delay line architectures for digitally controlled voltage regulators

2012 IEEE International SOC Conference, 2012

in my thesis committee. I am grateful for their comments and objective directions to complete the master's thesis work. I would also like to thank my mentor Harish Krishnamurthy from Intel Circuit Research Labs (CRL) for his help and support initiating this research. I appreciate his advice and enthusiastic help that definitely light up my road during my internship at Intel. I would also like to thank Yorgos, George Matthew, and Stefano, with Intel Corporation, for their helpful discussions. Last but not least, I would like to extend my gratitude to the people who have helped and inspired me during my research. My heartfelt appreciation goes toward my family and my dearest parents. They were always supportive whenever it was a hard time for me. I would like to thank my friends and colleagues especially Ahmed, Moataz, Kareem, Ahmed Mahfouz, and Ramy for their support and for the decent environment that we had in our lab.