Consistent model for short-channel nMOSFET after hard gate oxide breakdown (original) (raw)

Abstract

Dissimilar post-hard-breakdown nMOSFET characteristics are consistently explained by the location of a constant-size breakdown path. Device simulations with the breakdown path modeled as a narrow inclusion of highly doped n-type silicon well reproduce all postbreakdown nFET characteristics, including the substrate current behavior, for both gate-to-substrate and gate-to-extension breakdowns. An equivalent circuit describing the gate current in an nFET after hard gate-oxide breakdown is proposed.

Figures (10)

Fig. 1. Sorting s-values (1) measured on n = 100 E = 0.20 jem nFETs at Ve = —1.5 V gives the absolute positions x of the breakdown spots on the respective devices (2), provided the breakdown spots are randomly distributed along the entire gate length L. Inset: FET/breakdown path geometry.

Fig. 1. Sorting s-values (1) measured on n = 100 E = 0.20 jem nFETs at Ve = —1.5 V gives the absolute positions x of the breakdown spots on the respective devices (2), provided the breakdown spots are randomly distributed along the entire gate length L. Inset: FET/breakdown path geometry.

Fig. 2. Emission microscope images of 16 L = 10 ym nFETs after gate-oxide breakdown taken at V;, between 2 and 3 V (a) ordered randomly and (b) sorted according to parameter s determined on each FET. (c) Parameter s is a unique monotonic function of the breakdown spot position x detemined from (a) for each of the 16 FETs. Approximately equidistant spacing between ordered breakdown positions is apparent in (b) and (c).

Fig. 2. Emission microscope images of 16 L = 10 ym nFETs after gate-oxide breakdown taken at V;, between 2 and 3 V (a) ordered randomly and (b) sorted according to parameter s determined on each FET. (c) Parameter s is a unique monotonic function of the breakdown spot position x detemined from (a) for each of the 16 FETs. Approximately equidistant spacing between ordered breakdown positions is apparent in (b) and (c).

Fig. 3. Effective gate postbreakdown resistance (a) measured on 100 L = 0.20 ym nFETs can be deconvoluted as (b) a function of the breakdown position. R~ increases by a factor of ~ 20 for breakdowns above the FET channel. Both the MEDICI (line) and the SPICE (open squares) calculations using, respectively, the proposed physical model and the equivalent circuits for an nFET after hard gate breakdown fit the distribution well.

Fig. 3. Effective gate postbreakdown resistance (a) measured on 100 L = 0.20 ym nFETs can be deconvoluted as (b) a function of the breakdown position. R~ increases by a factor of ~ 20 for breakdowns above the FET channel. Both the MEDICI (line) and the SPICE (open squares) calculations using, respectively, the proposed physical model and the equivalent circuits for an nFET after hard gate breakdown fit the distribution well.

Fig. 5. Potential distributions and current flowlines calculated with MEDICI for gate-to-extension (2 = 0 sm) breakdown at Vg = Vp = Vy = 0 V and (a) V¢ = —1.5 V and (b) Ve = 1.5 V, and for gate-to-substrate (2 = 0.5L) breakdown at (c) Ve = —1.5 V and (d) Ve = 1.5 V. (a)-(b) Electrons are driven through the breakdown path by the electric field across the path. (c) Electrons are emitted from the gate, diffuse through the substrate and are collected at the source and the drain (bipolar effect). (d) Electrons flowing from source and drain in the channel controlled by the gate are pulled through the breakdown path into it (FET effect). Fig. 4. (a)-(e) Postbreakdown measurements on E = 0.20 yxm nFETs with hard breakdown located at the given x. (f)-(j) MEDICI simulation with 5 nm wic breakdown path at the corresponding «. Sublinear behavior of J, in (f) and (j) is ascribed to current crowding in the MEDICI simulation. (k)-(0) SPICE calculatic using the circuits in Fig. 6 with Ryo: fixed at 1 kQ.

Fig. 5. Potential distributions and current flowlines calculated with MEDICI for gate-to-extension (2 = 0 sm) breakdown at Vg = Vp = Vy = 0 V and (a) V¢ = —1.5 V and (b) Ve = 1.5 V, and for gate-to-substrate (2 = 0.5L) breakdown at (c) Ve = —1.5 V and (d) Ve = 1.5 V. (a)-(b) Electrons are driven through the breakdown path by the electric field across the path. (c) Electrons are emitted from the gate, diffuse through the substrate and are collected at the source and the drain (bipolar effect). (d) Electrons flowing from source and drain in the channel controlled by the gate are pulled through the breakdown path into it (FET effect). Fig. 4. (a)-(e) Postbreakdown measurements on E = 0.20 yxm nFETs with hard breakdown located at the given x. (f)-(j) MEDICI simulation with 5 nm wic breakdown path at the corresponding «. Sublinear behavior of J, in (f) and (j) is ascribed to current crowding in the MEDICI simulation. (k)-(0) SPICE calculatic using the circuits in Fig. 6 with Ryo: fixed at 1 kQ.

Fig. 6. (a) Equivalent circuit for an nFET with gate-to-channel breakdown. F represents the unbroken nFET. This circuit collapses (b) for 2 — 0 jm to the gate-to-source extension breakdown and (c) fora — L to the gate-to-drain extension breakdown.

Fig. 6. (a) Equivalent circuit for an nFET with gate-to-channel breakdown. F represents the unbroken nFET. This circuit collapses (b) for 2 — 0 jm to the gate-to-source extension breakdown and (c) fora — L to the gate-to-drain extension breakdown.

AN ve Neersgiecer received We M.o, Gegree if physics from the University of Gent, Belgium, in 1984. She joined IMEC in 1985, working on process modeling. She has been involved in modeling and simulation work for several European projects such as STORM (implantation and diffusion modeling in silicon, diffusion in silicides), ADEQUAT, ACE, and HUNT (process and device simulation for CMOS). At present she is mainly focussing on process and device simulation and calibration of 0.13um and smaller CMOS technologies. Next to this she is also esponsible for support of TCAD tools used at IMEC.

AN ve Neersgiecer received We M.o, Gegree if physics from the University of Gent, Belgium, in 1984. She joined IMEC in 1985, working on process modeling. She has been involved in modeling and simulation work for several European projects such as STORM (implantation and diffusion modeling in silicon, diffusion in silicides), ADEQUAT, ACE, and HUNT (process and device simulation for CMOS). At present she is mainly focussing on process and device simulation and calibration of 0.13um and smaller CMOS technologies. Next to this she is also esponsible for support of TCAD tools used at IMEC.

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