Consistent model for short-channel nMOSFET after hard gate oxide breakdown (original) (raw)
Related papers
Explanation of nMOSFET substrate current after hard gate oxide breakdown
Microelectronic Engineering, 2001
The origin of the substrate current in nMOSFET after hard gate oxide breakdown is studied as a function of the breakdown position. The breakdown path is modeled by a narrow ( | 5 nm diameter) inclusion of highly doped n-type silicon in SiO . Device simulations excellently reproduce all post-breakdown nMOSFET characteristics, including the substrate 2 current behavior, for both gate-to-substrate and gate-to-extension breakdowns. The model also identifies the origin of impact ionization and recombination observed in emission spectra.
32nd European Solid-State Device Research Conference, 2002
breakdown-position dependence of normalized currents in nFETs with 2.4 nm gate oxide is observed after soft and hard breakdowns. This suggests that electron energy is conserved in the soft breakdown path. It is concluded that the observed soft breakdown is best modeled by a lowered oxide barrier in the breakdown conduction path. The static behavior of an nFET immediately after SBD is discussed and tested using the MEDICI device simulator.
Modeling pFET currents after soft breakdown at different gate locations
Microelectronic Engineering, 2004
pMOSFET currents after soft gate oxide breakdown are studied as a function of the breakdown position. The analysis draws on analogies with post-soft breakdown processes in a nMOSFET. The pMOSFET breakdown path is modeled as a narrow region of SiO 2 with lower electron and hole barriers. MEDICI simulations of a pMOSFET after soft breakdown assuming preferential electron conduction through the breakdown path consistently explain the presented experimental data for both gate-to-substrate and gate-to-extension breakdowns.
Gate oxide breakdown in FET devices and circuits: From nanoscale physics to system-level reliability
Microelectronics Reliability, 2007
Gate oxide breakdown has been historically considered a catastrophic failure mechanism for CMOS technology. With CMOS downscaling the mid 1990's have seen the emergence of soft breakdown as a possible failure mode. At the same time the notion started appearing that the first breakdown event does not necessarily spell the immediate failure of the entire CMOS application. Relaxation of the CMOS circuit reliability criteria, however, requires a thorough understanding of the impact of the breakdown path on FET behavior. This cannot be consistently achieved without the microscopic perspective of the physical effects occurring in the affected device. Future CMOS applications will be able to sustain many soft breakdown events, which will be treated as additional parametric variation. Tools ranging from simulation to circuit monitoring will assure reliability at the functional level.
IEEE Transactions on Electron Devices, 2000
In state-of-the-art technologies, the currents in all n-channel field-effect transistor device terminals can be severely degraded when a soft or hard dielectric breakdown event occurs from gate-to-drain. The equivalent circuits that are commonly used for modeling gate-to-drain breakdown do not adequately capture all of the salient features of post breakdown device characteristics and can yield results that are overly optimistic. We present an equivalent circuit comprehending both soft and hard breakdown that can be used to accurately model gate, drain, and source currents following a breakdown event from gate-to-drain.
IEEE Transactions on Electron Devices, 2005
The post-breakdown (BD) degradation of ultrathin gate oxide Si MOSFET devices is studied by electrical characterization, cross-sectional transmission electron microscopy (TEM) analysis, and theoretical simulation. It is shown that MOSFET devices can remain functional even if a physically direct short between the gate electrode and Si substrate is established. On the other hand, a device can suffer from total failure while no physical damages can be observed under TEM. The physical location of the BD point is shown to be of critical importance in determining the type of BD and the post-BD electrical characteristics of the device. The ability to precisely categorize the gate oxide BD modes in narrow MOSFETs enables us to reevaluate the impact of the gate dielectric BD on the post-BD device performance, and its influence at the circuit levels.
IEEE Electron Device Letters, 2000
In this letter, we report new findings in the relation between channel hot-carrier (CHC) degradation and gate-oxide breakdown (BD) in short-channel nMOSFETS biased at . We observe that the time-to-BD is strongly reduced in the hot carrier regime and that although the channel hot-electron injection into the oxide occurs mainly at the drain side, stress-induced leakage current (SILC) generation and oxide BD always occur at the source side. The results of these measurements indicate that not solely the energy of the injected electrons but also the oxide electric field is determinant in the oxide BD process.
IEEE Transactions on Device and Materials Reliability, 2003
A comparative study of oxide breakdown in shortchannel nMOSFETs and pMOSFETs stressed at high voltages in inversion and in accumulation regimes is reported. We show that in all cases the breakdown location is uniformly distributed along the total channel length, indicating a uniform breakdown process independent of the dopant type in the electrodes. At low stress voltages (i.e., at operating conditions) we expect the breakdown locations to be still uniformly distributed in devices operated in inversion, while occurring preferentially in the source and drain extensions in devices operated in accumulation. Furthermore, we find that the hard oxide breakdown occurs in the case of nMOSFETs stressed in inversion, while in all the other cases almost all the breakdowns are soft.
On the properties of the gate and substrate current after soft breakdown in ultrathin oxide layers
IEEE Transactions on Electron Devices, 1998
In this work we have studied soft breakdown (SBD) in capacitors and nMOSFET's with 4.5-nm oxide thickness. It is shown that for larger area devices gate current and substrate current as a function of the gate voltage after SBD are stable and unique curves, but for smaller area devices both currents become lower and unstable. This difference can be explained by the different energy available for discharging in the SBD path. It is shown that the SBD detection strongly depends on the test structure area. In nMOSFET's for positive gate polarity, the large increase in the substrate current at the SBD moment is proposed as a sensitive SBD detector. Two level fluctuations in the gate current are investigated at different voltages and are explained by means of a model where electron capture-emission in the traps of the SBD path induces local field fluctuations causing variations in the tunneling rate across the oxide. In the substrate current directly correlated two-level fluctuations are observed.