Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy (original) (raw)

Fault tolerant structures for nanoscale gates

2007 7th IEEE Conference on Nanotechnology (IEEE NANO), 2007

Predicted device reliability for nanoelectronics indicates that redundant design will be necessary to build reliable nanosystems. Up to date, several fault tolerant techniques have been proposed and analyzed. However, the fabrication complexity of those circuits, which directly affects the final circuit reliability, is not usually considered. In this paper, we compare two fault tolerant techniques, NAND Multiplexing (NM) and Averaging Cells (AC), as possible solutions to improve the nanoscale gate reliability. First, we propose nanodevice specific layouts for the two techniques. Then, we introduce nanotechnology oriented models to evaluate the area cost and reliability of the gates. Our simulations indicate that NM based gates are more reliable than AC gates when the error probabilities of the circuit parts are lower than 0.003. However, when this value is exceeded (which is expected for electronic nanotechnologies) AC gates are more reliable at a lower area cost.

A Fault Tolerant Threshold Logic Gate Design

wseas.us

Threshold Logic gate is used as design abstraction for most nano devices and perceived as an alternate emerging technology to CMOS implementation. It is vulnerable to manufacturing inaccuracies that alter weight values which inadvertently affect the functionality of the gate. Hence fault tolerance should be taken in to consideration during the design of threshold logic gates to tolerate manufacturing defects to the maximum possible extent. In this work, a fault tolerant design methodology for threshold logic gate is presented.

A defect- and fault-tolerant architecture for nanocomputers

Nanotechnology, 2003

Both von Neumann's NAND multiplexing, based on a massive duplication of imperfect devices and randomized imperfect interconnects, and reconfigurable architectures have been investigated to come up with solutions for integrations of highly unreliable nanometre-scale devices. In this paper, we review these two techniques, and present a defect-and fault-tolerant architecture in which von Neumann's NAND multiplexing is combined with a massively reconfigurable architecture. The system performance of this architecture is evaluated by studying its reliability, i.e. the probability of system survival. Our evaluation shows that the suggested architecture can tolerate a device error rate of up to 10 −2 , with multiple redundant components; the structure is efficiently robust against both permanent and transient faults for an ultra-large integration of highly unreliable nanometre-scale devices.

A fault-tolerant technique for nanocomputers: NAND multiplexing

2002

In order to make systems based on nanometerscale devices reliable, the design of fault-tolerant architectures will be necessary. This paper presents a novel fault-tolerant technique for future nanocomputers, NAND multiplexing. Initiated by von Neumann, the NAND multiplexing technique, based on a massive duplication of imperfect devices and randomized imperfect interconnect, had been studied with an extreme high degree of redundancy (A 4333). In this paper, the NAND multiplexing is extended to rather low degree of redundancy, leading it to a comprehensive fault-tolerant theory. The stochastic Markov nature in the heart of the system is discovered, and the characteristics of such a Markov chain are exploited. This fault-tolerant technique is potentially useful for future nanoelectronics.

Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics

IEEE Design and Test of Computers, 2005

328 0740-7475/05/$20.00 © 2005 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers THERE IS RENEWED INTEREST in using hardware redundancy to mask faulty behavior in nanoelectronic components. In this article, we go back to the early ideas of von Neumann and review the key concepts behind Ntuple modular redundancy (NMR), hardware multiplexing, and interwoven redundant logic. We discuss several important concepts for redundant nanoelectronic system designs based on recent results. First, we use Markov chain models to describe the error-correcting and stationary characteristics of multiple-stage multiplexing systems. Second, we show how to obtain the fundamental error bounds by using bifurcation analysis based on probabilistic models of unreliable gates. Third, we describe the notion of random interwoven redundancy. Finally, we compare the reliabilities of quadded and random interwoven structures by using a simulation-based approach. We observe that the deeper a circuit's logical depth, the more fault-tolerant the circuit tends to be for a fixed number of faults. For a constant gate failure rate, a circuit's reliability tends to reach a stationary state as its logical depth increases.

Analysis of reliability for fault tolerant design in NANO CMOS logic circuit

Experimental and Theoretical NANOTECHNOLOGY

The emerging nano scaled electronic devices are Carbon Nanotubes (CNT), Silicon nanowires (SINW), nano CMOS switches etc. In Nano CMOS switches, the devices can be interconnected to build the nano scaled CMOS circuit. In this nano CMOS circuit, faults occur at three levels, such as gate level, circuit level and switch level. This paper focusses on the switch level faults of stuck-open or stuck-off and stuck-short or stuck-on that frequently occurs in CMOS switches. To overcome the switch level faults and to increase the reliability, the fault tolerant technique known as the Quadded Transistor (QT) structure is used. An analytical model has been formulated to determine the probability of failure by analyzing the stuck open and stuck short faults. Also, the model has been formulated by implementing QT structure for the single CMOS NAND2 gate. By the use of analytical formulations, the results has been simulated for the occurrence of minimum to maximum number of defective transistors i...

Fault-tolerant programmable logic array for nanoelectronics

International Journal of Circuit Theory and Applications, 2012

This paper presents the architecture for a nanoelectronic logic system in which a regular array of logic gates with programmable interconnections is accompanied by a data transmitter and receiver as well as program registers and a controller. Binary programmable interconnections assure system versatility by providing the means of computing different logic operations. They also allow setting the redundancy level via the number of columns clustered to compute a certain function. A system operation is explained and visualized with a number of examples. The embedded scheme of fault tolerance can effectively mitigate permanent, as well as transient, faults. Some implementation and performance aspects are approached through simulations of single-electron tunneling structures. However, the proposed architectural concept is generic and can be applied to systems implemented with alternative nanotechnologies.

Design of fault tolerant majority voter for error resilient TMR targeting micro to nano scale logic

International Journal of Computational Science and Engineering, 2020

The shrinking size of transistors for satisfying the increasing demand for higher density and low power has made the VLSI circuits more vulnerable to faults. Therefore, new circuits in advanced VLSI technology have forced designers to use fault tolerant techniques in safety-critical applications. Also, the presence of some faults (not permanent) due to the complexity of the nanocircuit or its interaction with software results in malfunctioning of circuits. The fault tolerant scheme, where majority voter plays the core role in triple modular redundancy (TMR), is being implemented increasingly in digital systems. This work targets to implement a different fault tolerant scheme of majority voter for the implementation of TMR using quantum-dot cellular automata (QCA), viable alternative nanotechnology to CMOS VLSI. The fault masking ability of various voter designs has been analysed in details. The fault masking ratio of the proposed voter (FMV) is 66% considering single/multiple faults. Simulation results establish the validation of proposed logic in QCA which targets nano-scale devices. The proposed logic is also suitable for conventional CMOS technology, which is verified with the Cadence tool.

A clock-fault tolerant architecture and circuit for reliable nanoelectronics system

2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2007

Due to discrepancies in manufacturing process and the probabilistic nature of quantum mechanical phenomenon, nanoelectronic devices cannot be made as reliable as current microelectronic devices. As a result, fault-tolerant architectures are a prerequisite to building reliable electronic systems from these unreliable nanoelectronic devices. One important design aspect of nanoelectronic architecture that demands attentive consideration is clock generation and distribution. Various defects and interference such as doping discrepancies, supply noise and cross-talks could lead to clock irregularity and malformed clock signals, thus resulting in faulty operations of sequential circuits. Generally, these errors are not readily amenable to efficient correction using error-correcting codes known to date.

On fault tolerance techniques towards nanoscale circuits and systems

2005

The move towards nanoscale circuits poses new challenges to circuit design. As the dimensions shrink, it is becoming increasingly difficult to control the variance of physical parameters in the manufacturing process, for instance the concentration of dopants, the thickness of the gate and the insulation oxides, the width and thickness of metal wires, etc. This results in decreased yield which increases the costs per functioning chip. Electromigration causes intermittent and permanent failures after some period of operation, which means that these faults cannot be observed in the manufacture test. The problem of electromigration increases when going further to nanometer regime because of the decreasing width and increasing deviation of wires. Lowering the supply voltages make the circuits more vulnerable to noise and background radiation resulting in a higher soft error rate.