(Invited) Wafer Scale Copper Direct Plating on Thin PVD RuTa Layers: A Route to Enable Filling 30 nm Features and Below (original) (raw)
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Journal of The Electrochemical Society
Among all the Ru-based substrates, mixed-phase RuTa liners grown by physical vapor deposition have been explored as potential directly-platable diffusion barrier candidates. In order to understand the full-wafer copper direct plating process that occurs on these liners, the effect of the applied waveform, electrical contacts and suppressor chemistry have been investigated. In order to enhance copper nucleation and wafer scale edge-to-center copper front propagation rate, a liner surface cleaning protocol is developed. The copper front propagation across the 300 mm wafer is reported as a function of the RuTa film thickness. An optimized copper direct plating process on RuTa layers as thin as 4 nm is integrated in 90 and 30 nm half pitch single and dual damascene structures. Results in terms of compatibility of the direct plated copper with the following chemical mechanical planarization step complemented with physical and electrical characterization data are reported. The direct fill...
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2011
A study has been carried out to understand the mechanism that enables plasma enhanced atomic layer deposition ͑PEALD͒-grown RuTaN barriers to support direct ͑seedless͒ copper electroplating. In particular, the effects of changing the liner surface chemistry on the subsequent plated copper nucleation behavior have been evaluated. Amperometric measurements and short pulse plating experiments were carried out directly on PEALD-grown RuTaN barriers. To enhance copper nucleation, a liner surface cleaning protocol was developed and evaluated. In order to understand the effect of intrinsic liner composition and conductivity on the film microstructure and subsequent plated copper nucleation, a study of copper nucleation density as it relates to the Ru:Ta ratio in the liner was carried out. The thickness extendibility of these direct plate liners was also explored. These liners were also tested for potential use in sub-45-nm copper metallization applications.
A Bilayer Diffusion Barrier of ALD-Ru/ALD-TaCN for Direct Plating of Cu
Journal of The Electrochemical Society, 2008
Diffusion barrier performances of atomic layer deposited ͑ALD͒-Ru thin films between Cu and Si were improved with the use of an underlying 2 nm thick ALD-TaCN interlayer as diffusion barrier for the direct plating of Cu. Ru was deposited by a sequential supply of bis͑ethylcyclopentadienyl͒ruthenium ͓Ru͑EtCp͒ 2 ͔ and NH 3 plasma and TaCN by a sequential supply of ͑NEt 2 ͒ 3 Ta = Nbu t ͑tert-butylimido-trisdiethylamido-tantalum͒, and H 2 plasma. Sheet resistance measurements, X-ray diffractometry, and Auger electron spectroscopy analysis showed that the bilayer diffusion barriers of ALD-Ru ͑12 nm͒/ALD-TaCN ͑2 nm͒ and ALD-Ru ͑4 nm͒/ALD-TaCN ͑2 nm͒ prevented the Cu diffusion up to annealing temperatures of 600 and 550°C for 30 min, respectively. This is because of the excellent diffusion barrier performance of the ALD-TaCN film against the Cu, due to its amorphous structure. A 5 nm thick ALD-TaCN film was even stable up to annealing at 650°C between Cu and Si. Transmission electron microscopy investigation, combined with energy-dispersive spectroscopy analysis, revealed that the ALD-Ru/ALD-TaCN diffusion barrier failed by the Cu diffusion through the bilayer into the Si substrate. This is due to the ALD-TaCN interlayer preventing the interfacial reaction between the Ru and Si.
Electrodeposition of Cu on Ru Barrier Layers for Damascene Processing
Journal of The Electrochemical Society, 2006
Superfilling of submicrometer trenches by direct copper electrodeposition onto physical vapor deposited and atomic layer deposited Ru barriers is demonstrated. The Cu nucleation and growth mode is found to be sensitive to the oxidation state of the Ru surface as well as the copper deposition parameters. Depending on the processing conditions, Cu deposition may or may not occur competitively with oxide reduction. Failure to remove the air-formed 3D oxide film results in Volmer-Weber ͑island͒ growth and consequently poor trench filling, as well as poor adhesion between Cu and Ru. In the case of thin resistive oxide-covered Ru seed layers, the "terminal effect" further exacerbates the difficulties in obtaining a compact, fully coalesced Cu film because the rate of Ru oxide reduction is decreased along with the density of Cu nuclei. In contrast, Cu deposition on a reduced "oxide-free" Ru surface results in more rapid coalescence involving the formation of a wetting Cu underpotential deposition layer. Electrochemical reduction of the oxidized Ru seed layer in a deaerated sulfuric acid solution, followed by rapid wet transfer to a Cu plating bath, enables robust superfilling of trenches and improved adhesion between Cu and Ru. Early film coalescence is favored by deposition at high ͑ Ϸ-0.25 V͒ overpotentials.
Influence of diffusion barriers on the nucleation and growth of CVD Cu for interconnect applications
Microelectronic Engineering, 2000
Nucleation and growth behavior of Cu influence strongly the macroscopic properties of the resultant films. In this work the nucleation of CVD Cu on different underlayer materials is studied. It is found that nucleation on bare diffusion barrier surfaces leads to island growth and, therefore, bad wetting and adhesion. An enrichment of F, O and carbon was found at the interface between the CVD Cu film and the diffusion barrier. However CVD Cu deposited on top of Ta with a 200-A PVD Cu layer on top results in good wetting. CVD Cu films grown on a PVD Cu layer expose a highly preferred k111l orientation. In this case SIMS analysis reveals a comparably low concentration of oxygen, carbon and flourine at the interface region between the CVD Cu and the barrier. These observations shed light on relevance of surface conditions for the CVD Cu deposition process. They significantly affect both film adhesion and crystal orientation, which are crucial for the use of CVD Cu as interconnect material.
2011
The diffusion barrier properties of PVD Ru and PECVD / PEALD Ru-C films, deposited by RuEtcp 2 precursor and N 2 /H 2 plasma, were compared on the basis of bias temperature stress measurements. An MIS test structure was used to distinguish between thermal diffusion induced by annealing and a Cu field drift due to applied electric fields. BTS-CV, TZDB and TDDB measurements revealed that the barrier performance is significantly better for PEALD and PECVD Ru-C films. This improvement is associated with carbon impurities in the Ru films with a concentration in the order of several percent according to ToF-SIMS and ERDA. The TDDB mean time to failure at 250°C, +5 MV/cm was 7 s for PVD Ru samples, %500 s for PECVD Ru-C, %800 s for PEALD Ru-C and >3600 s for PVD TaN. Triangular voltage sweep measurements at 300°C, 0.1 V/s confirmed the presence of Cu ions inside the SiO 2 for degraded dots, in contrast to the Al reference sample and to PVD TaN, which performed best among all the Cu barriers under test. XRD data suggests that PEALD and PECVD Ru-C films are only weakly crystalline.
Journal of The Electrochemical Society, 2011
Extending copper electrochemical deposition to 3× nm nodes and beyond requires a new plating approach that is not constrained by typical PVD copper seed step coverage performance. To this purpose, we propose a copper direct plating process on Plasma Enhanced Atomic Layer Deposition (PEALD) Ru-based resistive substrates, where the Cu seed is deposited in-situ during the front propagation from the edge to the center of the wafer. In order to understand the full-wafer copper direct plating process that occurs on these liners, the effect of plating tool segmented anode, applied waveform, plating chemistry and substrate surface activation on the subsequent plated copper nucleation and propagation behavior are studied. 7 8 9 10 11 12
Size reduction of the barrier and liner stack for copper interconnects is a major bottleneck in further down-scaling of transistor devices. The role of the barrier is to prevent diffusion of Cu atoms into the surrounding dielectric, while the liner (also referred to as a seed layer) ensures that a smooth Cu film can be electroplated. Therefore, a combined barrier+liner material that restricts the diffusion of Cu into the dielectric and allows for copper electro-deposition is needed. In this paper, we have explored barrier+liner materials composed of 1 and 2 monolayers (MLs) of Ru-passivated epsilon-TaN and Ru doped epsilon-TaN and focus on their interactions with Cu through the adsorption of small Cu clusters with 1-4 atoms. Moreover, different doping patterns for Ru doping in TaN are investigated to understand how selective doping of the epsilon-TaN surface influences surface stability. We found that an increased concentration of Ru atoms in the outermost Ta layer improves the adhe...
Gap filling with PVD processes for copper metallized integrated circuits
Microelectronic Engineering, 1997
The paper presents the results of two PVD techniques used for trench and via filling in copper-based metallization systems. The structure size is scaled down to 0.5 p,m and the aspect ratio (ratio of depth to width) is coming up to about 2.5. The patterning of the copper lines is performed by CMP (damascene technique). The first dc magnetron sputtering is optimized for trench filling with aspect ratios up to 1 by using variation of the distance between the substrate and the sputter target. It is shown that this variation is more effective for getting better filling results in comparison with variation of the deposition parameters like dc power, substrate temperature and substrate rf bias. Besides alternative investigated filling techniques like copper reflow, copper self-sputtering or ICP/ECR-based ionised sputtering the second high current pulsed arc deposition is performed to reach void-free filled vias and trenches with aspect ratios of 2. The typical problem with droplets is minimized. The first results show that the performance of this PVD technique is comparable with those of the above-mentioned filling methods and with copper CVD too. Additionally, it seems possible to use the deposition process in such a way that a Ta diffusion barrier can be deposited either conformally or without a noticeable layer growth on the top of the structure.
TiN-CVD process optimization for integration with Cu-CVD
Microelectronic Engineering, 2000
Integration of Cu-CVD as metallization for on-chip interconnect requires an efficient barrier to avoid any Cu diffusion in the insulating material. These barriers must also promote adhesion of Cu to the inter-and intra-metal level material, and have low resistivity to minimize level to level contact resistance. This paper discusses about the performance of Cu-CVD via integrated with TiN-CVD barrier in Cu / SiO interconnection structures. After a review of the TiN-CVD performance as a 2 diffusion barrier, Cu-CVD adhesion properties will be evaluated as a function of both TiN and Cu deposition process and TiN surface treatments. In addition to the standard tape test method, wettability after annealing of a thin Cu-CVD film deposited on the TiN barrier was studied to characterize adhesion of Cu-CVD to the barrier under evaluation. The presence of fluorine and fluorinated compounds were observed at the Cu / TiN interface, due to Cu-CVD deposition process based on Cupraselect. The major impact of such contamination on adhesion and TiN barrier resistivity will be evidenced. Finally, electrical results are given for two-level Cu interconnections performed in a dual damascene architecture. Very low via chain resistances are obtained after optimization of the TiN-CVD/ Cu-CVD process integration.