Structural and Electrical Characterization of ZnO Films Grown by Spray Pyrolysis and Their Application in Thin-Film Transistors (original) (raw)
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Using a ceramic target ZnO:In with In doping concentration of 2%, hetero-junctions of n-ZnO:In/p-Si and p-ZnO:(In, N)/n-Si were fabricated by depositing Indium doped n-type ZnO (ZnO:In or IZO) and Indium-nitrogen co-doped p-type ZnO (ZnO:(In, N)) films on wafers of p-Si (100) and n-Si (100) by DC magnetron sputtering, respectively. These films with the best electrical and optical properties were then obtained. The micro-structural, optical and electrical properties of the n-type and p-type semiconductor thinfilms were characterized by X-ray diffraction (XRD), RBS, UV-vis; four-point probe resistance and room-temperature Hall effect measurements, respectively. Typical rectifying behaviors of p-n junction were observed by the current-voltage (I-V) measurement. It shows fairly good rectifying behavior with the fact that the ideality factor and the saturation current of diode are n=11.5, Is=1.5108.10-7 (A) for n-ZnO:In/p-Si hetero-jucntion; n=10.14, Is=3.2689.10-5 (A) for p-ZnO:(In, N)/n-Si, respectively. These results demonstrated the formation of a diode between n-type thin film and p-Si, as well as between p-type thin film and n-Si..
Structural changes during the reaction of Ni thin films with (100) silicon substrates
Acta Materialia, 2012
Ultrathin films of nickel deposited onto (1 0 0) Si substrates were found to form kinetically constrained multilayered interface structures characterized by structural and compositional gradients. The presence of a native SiO 2 on the substrate surface in tandem with thickness-dependent intrinsic stress of the metal film limits the solid-state reaction between Ni and Si. A roughly 6.5 nm thick Ni film on top of the native oxide was observed regardless of the initial nominal film thickness of either 5 or 15 nm. The thickness of the silicide layer that formed by Ni diffusion into the Si substrate, however, scales with the nominal film thickness. Cross-sectional in situ annealing experiments in the transmission electron microscope elucidate the kinetics of interface transformation towards thermodynamic equilibrium. Two competing mechanisms are active during thermal annealing: thermally activated diffusion of Ni through the native oxide layer and subsequent transformation of the observed compositional gradient into a thick reaction layer of NiSi 2 with an epitaxial orientation relationship to the Si substrate; and, secondly, metal film dispersion and subsequent formation of faceted Ni islands on top of the native oxide layer.
Microelectronic Engineering, 2008
Nickel oxide Resistive switching X-ray reflectivity Grazing incidence X-ray diffraction Time of flight secondary ion mass spectrometry a b s t r a c t Thin NiO films, included in a metal/resistive oxide/metal (MRM) stack, are receiving great interest, as they exhibit resistive switching when subjected to an external applied field, and can thus be implemented in a resistive random access memory (ReRAM). The electrical switching characteristic is seen to depend on the NiO/metal coupling. Therefore a characterization of the interface between NiO and the electrode is vital to optimize and get insights on the switching phenomena. In this work we deposited NiO thin films by atomic layer deposition (ALD) at 300°C and electron beam deposition (e-beam) at 40°C on Si, Ni, Pt, W and TiN substrates and we characterized them with X-ray reflectivity (XRR), grazing incidence X-ray diffraction (GIXRD) and time of flight secondary ion mass spectrometry (ToF-SIMS). Depending on the growth process, we found an influence of the substrate on the NiO film roughness, which exhibits values in the 1.2-6.2 nm range. NiO electron density was 1.35-1.96 e À Å À3 spread around the nominal value of 1.83 e À Å À3 for bulk cubic polycrystalline NiO. X-ray diffraction showed that NiO is polycrystalline in the cubic phase. ToF-SIMS profiles confirm NiO/Metal interface sharpness and the optimal uniformity of NiO layers. Intermixing phenomena are limited or absent and the presence of contaminants, such as C, F, and Cl is very low.
MRS Proceedings, 2012
ABSTRACTTransparent p-n hetero-junction diodes are fabricated using, p-type NiO and n-type ZnO thin films deposited onto a Pt/Ti/glass substrate utilizing RF sputtering technique. The prepared hetero-junctions are studied for the structural, electrical and optical properties and the effect of post-deposition annealing is investigated through I-V measurements and XRD analysis. The as deposited hetero-junction is found to be giving ohmic behaviour while with post-annealing treatment it result in rectification with a ratio of forward-to-reverse current as high as 15 in the range -1.0 to 1.0 V. Forward threshold and the reverse breakdown voltages are found to be about 0.5 and -2.7 V, respectively. The forward-bias I-V characteristics are dominated by the flow of space-charge-limited current with an optical transmission of above 50 % in the visible region important for the transparent electronic device fabrication.
Exploration of ZnO and ZnMgO/ZnO Thin Film Transistors
2015
Transparent semiconductor technology can improve the performance of thin film transistors (TFTs) in flat panel displays, making the product more energy efficient and cost effective. To achieve this, it is necessary to replace the commonly used material amorphous silicon (a-Si) with materials that have more suitable properties. With its large direct bandgap (3.3 eV at room temperature) and high exciton binding energy (60 meV), zinc oxide (ZnO) emerges as an attractive candidate for this kind of application. The present thesis explores TFTs made of ZnO and zinc magnesium oxide (ZnMgO) deposited with metal-organic chemical vapor deposition. Xray diffraction (XRD) was used to investigate the crystallinity of the ZnMgO/ZnO samples. Further, two types of transistors have been considered. The first type makes use of ZnO as the channel material on a silicon substrate with silicon oxide (SiO 2) or silicon nitride (Si 3 N 4) as gate dielectric, i.e. adapting so called bottom gate device architecture. The second type is a ZnMgO/ZnO hetero-structure TFT made on r-and c-sapphire as substrates with a top gate design. The hetero-structure fabricated on c-sapphire exhibited characteristics indicating the formation of a two-dimensional electron gas at the ZnMgO/ZnO interface due to its polar growth direction. On the other hand, the hetero-structure grown on r-plane has non-polar growth direction; no 2DEG at the interface. Plasma-enhanced chemical vapor deposition (PECVD) was used for deposition of the dielectrics to avoid the high concentration of fixed charges that was likely to result from thermal oxidation of boron doped p-type silicon wafers (N a ≈ 10 15 cm-3). Insulator thickness and refractive index was measured by ellipsometry to check on the film quality and this varied with deposition parameters. C-V characterization was used to study the properties of the insulating layers by fabricating metal-insulator-semiconductor structures and optimal temperature, RF power and reactor pressure was found for deposition of SiO 2. In contrast, the results obtained from C-V measurements for optimal growth conditions of Si 3 N 4 were less definite. IV measurements performed on the TFTs generally show a higher performance for transistors with SiO 2 as gate dielectric than with Si 3 N 4. Threshold voltage, field effect mobility and on/off current ratio for the bottom gate TFTs were calculated from I-V characteristics and the TFTs show superior device characteristics. For the ZnMgO/ZnO TFTs the mobility ranged from 0.3 to 170 cm 2 /Vs, with transistors on c-sapphire having higher mobility than those on r-sapphire, a fact attributed to the formation of a 2DEG. Threshold voltages were 2-4 V and on/off current ratios were in the range 10 3-10 4 for ZnMgO/ZnO TFTs. v I would like to thank my supervisor Andrej Kuznetsov for his insight and vision for my thesis. Vishnukanthan Venkatachalapathy helped me a great deal with setting up the working plan and with training on X-ray diffraction. He also did all depositions of ZnO and ZnMgO with MOCVD. I am indebted to him for his contribution. I would also like to thank both Viktor Bobal and Mikael Sjödin for training on several instruments and their frequent help in the MiNalab, without which the work in the laboratory would have been much more difficult. In addition I am grateful to Per Lindberg for his help with I-V measurements among other things and his willingness to always lend a helping hand or explain something to me if I did not understand it. Vincent Quemener gave me training for laser cutting and thermal evaporation. I thank him for that and for his helpful and friendly attitude. Others that have helped me during the work with my thesis are Naoya Iwamoto, Pekka Neuvonen and Ilia Kolevatov. I am thankful for all their help. Finally I would like to thank Bengt Gunnar Svensson who through his course on semiconductor components introduced me to the field of semiconductor physics and with his enthusiasm inspired me to dive into this field and learn more about it.
Electrical characterization of low temperature deposited oxide films on ZnO/n-Si substrate
Bulletin of Materials Science
Thin films of silicon dioxide are deposited on ZnO/n-Si substrate at a low temperature using tetraethylorthosilicate (TEOS). The ZnO/n-Si films have been characterized by atomic force microscopy (AFM) and scanning electron microscopy (SEM). The border trap density (Q bt ) and fixed oxide charge density (Q f /q) of the SiO 2 /ZnO/n-Si films are found to be 3⋅ ⋅9 × 10 10 cm -2 and 1⋅ ⋅048 × 10 11 cm -2 , respectively. The trapping characteristics and stress induced leakage current (SILC) have also been studied under Fowler-Nordheim (F-N) constant current stressing.