FPGA Based Implementation and Comparison of Beamformers for CDMA2000 (original) (raw)
Related papers
IET Microwaves, Antennas & Propagation, 2010
Software radio implementations of beamformers on programmable processors such as digital signal processor (DSP) and field programmable gate array (FPGA) still remain as a challenge for the integration of smart antennas into existing wireless base stations for 3G systems. This study presents the comparison of DSP-and FPGA-based implementations of space -code correlator (SCC) beamformer, which is practical to use in CDMA2000 systems. Implementation methodology is demonstrated and results regarding beamforming accuracy, weight vector computation time (execution time) and resource utilisation are presented. The SCC algorithm is implemented on Texas Instruments (TI) TMS320C6713 floating-point digital signal processors (DSPs) and Xilinx's VirtexIV family FPGA. In signal modelling, CDMA2000 reverse link format is employed. The results show that beamformer weights can be obtained within less than 10 ms via implementation on c6713 DSP with direction-of-arrival (DOA) search resolution of Du ¼ 28, whereas it can be achieved within less than 25 ms on VirtexIV FPGA for five-element uniform linear array (ULA). These results demonstrate that FPGA implementation achieves weight vector computation in much smaller time (nearly 500 times) as compared to DSP implementation in this study.
Software Radio Implementation of a Smart Antenna System on Digital Signal Processors for cdma2000
Lecture Notes in Computer Science, 2004
This paper presents a software defined radio (SDR) implementation based on programmable digital signal processors (DSP) for smart antenna systems (SAS). We evaluate adaptive beamforming algorithms, namely nonblind-type least mean square (LMS) and blind-type constant modulus (CM) using TI TMS320C6000 high performance DSPs for cdma2000 reverse link. Adaptive beamformers are implemented using TI code composer studio (CCS) that includes assembly language and C code development tools. Performance variation of these sofware radio beamformers in terms of weight computation time and received SINR are compared for different C6000 development boards (TMS320C6701 EVM, TMS320C6711 DSK, and TMS320C6713 DSK) and array topologies under varying multipath propagation conditions. Results show that while antenna array and algorithm type is important for the SINR performance, DSP type becomes important for the weight computation time.
FPGA Implementation of Beamforming Receivers Based on MRC and NC-LMS for DS-CDMA System
IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06), 2006
In this paper, we investigate a beamforming receivers based on maximum ratio combining (MRC) and noise constraint least mean square (NC-LMS) using rapid prototyping method for FPGA implementation. Non-adaptive and adaptive beamforming techniques approaches are considered. A performance evaluation of these algorithms in a DS-CDMA system is presented and FPGA design is evaluated in term of hardware resources for Xilinx family devices using rapid prototyping methodology with Matlab-Simulink tools. Both approaches offer a good performance-complexity tradeoff favorable for FPGA implementation. However, due to the adaptive approach, the NC-LMS presents a better robustness to the fixed point arithmetic than the MRC.
A Practical Space-Code Correlator Receiver for DSP Based Software Radio Implementation in CDMA2000
Wireless Personal Communications, 2009
Development of practical algorithms for beamforming in 3G CDMA systems and their software radio implementations are still a challenging task, which will facilitate upgrading of traditional base stations into smart antenna capable 3G base stations. In this paper, we propose a practical space-code correlator (SCC) receiver structure for its software radio implementation a DSP. SCC's advantage comes from the fact that it doesn't require any training sequence or learning parameter as in other algorithms (LMS or CM). DSP implementations of the SCC are performed using Texas Instruments C67xx family platforms. In the simulations, reverse link base band signal format of CDMA2000 is used and the effects of different array topologies (uniform linear array-ULA or uniform circular array-UCA) are considered. The implementation results regarding beamforming accuracy, weight vector computation time (execution time), search resolution effect on DOA estimation accuracy, DSP resource utilization, and received SINR are presented. The results show that DSP based SCC beamformer can estimate weight vectors within less than 10 ms with DOA search resolution of 2 • especially when C6713 DSP is used. With faster DSPs and 246 K. Kucuk et al. larger search resolutions, execution time could be significantly reduced as well. It provides comparable SINR performance with LMS and CM algorithms.
Digital Beamforming Implementation on an FPGA Platform
2007
Te diré algo que ya sabes. El mundo no es sol ni arco iris. Es un sitio muy malo y desagradable, y no importa lo duro que seas, te pondrá de rodillas y te dejará ahí permanentemente si se lo permites. Tú, yo, nadie pega más duro que la vida. Pero no se trata de lo duro que pegues. Se trata de cuan duro te peguen y puedas seguir adelante. Se trata de cuanto aguantas y sigues adelante. Así es como se gana! Si sabes lo que vales, sal a buscarlo. Pero tienes que estar dispuesto a soportar los golpes. Y no acusar a nadie diciendo que no eres lo que quisieras por culpa de aquel, o de aquella o de nadie. Los cobardes hacen eso, y tú no eres un así! Eres mejor que eso! Siempre te querré no importa lo que pase. Thanks to all Contents Chapter 1 Introduction Chapter 2 State-of-the-art programmable devices for DSP implementation 2.1 Brief history of programmable devices 2.2 Digital Platforms 2.3 Virtex-5 LX220 application board Chapter 3 An Antenna Array Receiver for the S-DMB system 3.1 Signal characteristics of the S-DMB system 3.2 DBF Techniques 3.3 DBF Architecture and Digital Requirements Chapter 4 DBF Platform prototyping and implementation 4.1 Modes of operation 4.2 Detailed Block description of F P GA 1 4.3 Detailed Block description of F P GA 2 vii viii Contents 4.4 Hardware Requirements 4.5 Simulating data on an FPGA Chapter 5 Conclusions References LIST OF FIGURES xi 4.13 Simulation results of the Selection illuminated elements block. This graph only shows Pilot Symbol and its corresponding channel selection. 4.14 Simulation results of the Selection illuminated elements block. This Figure depicts the computation ofp vector (real and imaginary) for the 40 channels. 4.15 Simulation results of the Selection illuminated elements block. This graph shows the selection of 12 channels with its corresponding computedp vector and despreads. 4.16 Simulation results of the Selection illuminated elements block. This Figure shows the calculation of the 32 despreads (real and imaginary) for 1 channel. 4.17 Radiation pattern for the calculate weights. 4.18 DBF block: N p parallel I&Q arms processed at the F s rate. 4.19 Schematic description of the DBF block. 4.20 Internal operation of F P GA 2. 4.21 Matched Filter of 16 coefficients. 4.22 Schematic description for the I&Q correlator. 4.23 Schematic description for the F P GA 2. 4.24 Correlation of each sample and correlation modulus. 4.25 Correlation modulus. 4.26 Requeriments of F P GA 1. 4.27 Requeriments of F P GA 2. 4.28 Screen capture of the programmed MATLAB interface to obtain processed data from the FPGA. 2.2. Digital Platforms 9 2.2.1.3 Applications Applications of FPGAs include digital signal processor DSP, software-defined radio, aerospace and defense systems, ASIC prototyping, medical imaging, computer vision, speech recognition, cryptography, bioinformatics, computer hardware emulation and a growing range of other areas. FPGAs originally began as competitors to CPLDs and competed in a similar space. As their size, capabilities, and speed increased, FPGAs began to take over larger and larger functions to the state where some are now marketed as full systems on chips (SOC).
Performance of Smart Antennas with FPGA Signal Processors over 3G Antennas
Wireless Communication, 2010
Demands for increased capacity and better quality of service are driving the development of new wireless technologies such as “smart” antenna arrays. The FPGAs operate as powerful digital signal processing devices, which can meet the requirements of adaptive antenna arrays. The smart antenna systems are efficient than the existing 3G antenna systems as they can track the location of a mobile user and also increase channel capacity through spatial diversity. FPGAs offer greater flexibility for performing functions such as acquisition control, digital down-conversion, demodulation and matched filtering. This paper discuses in creating beam-forming smart antennas using FPGA’s as well as the ways in which smart antennas will overcome the performance of 3G antennas.
FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems
EURASIP Journal on Embedded Systems, 2006
Field-programmable gate arrays (FPGAs) are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs), through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs). In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single-and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.
This paper investigates the rapid prototyping of a multiple input-multiple-output direct sequence-code division multiple access (MIMO DS-CDMA) system with rake receiver, implemented on a field programmable gate array (FPGA) based hardware platform. The hardware implementation is created using the Altera DSP builder-a MATLAB/Simulink based system-level design tool and the Stratix EP1S80 DSP development board from Altera. The hardware-in-the-loop (HIL) co-simulation and the Logic Analyzer are used with the physical FPGA board implementing the design to evaluate the system performance and to verify the functionality of the hardware implementation in the MATLAB/Simulink environment. Results show that, in general, the bit error rate (BER) of the hardware implementation fell within the confidence intervals of the simulated BER. Index Terms-Rapid prototyping, FPGA, Hardware-in-the-loop, DS-CDMA, MIMO, Space-time coding, Rake receiver.
2000
In this paper, for cdma2000 reverse link, we evaluate the feasibility of implementation of two simple beamforming algorithms, namely non-blind type Least Mean Square (LMS) and blind-type Constant Modulus (CM) algorithms using Texas Instruments (TI) C6700 family floating point Digital Signal Prcessors (DSPs). Performance variation of these DSP-enabled beamformers in terms of weight computation time (convergence time) and received SINR
CDMA Based Wireless Transceiver System MATLAB Simulation and FPGA Implementation
2005 Student Conference on Engineering Sciences and Technology, 2005
Code Division Multiple Access (CDMA) has become the technology of choice for the current and future generation of wireless systems. We have implemented the CDMA IS-95 based Wireless Transceiver System using Matlab Simulink v 7.0. The entire system is implemented using the Xilinx System Generator Block v6.3. Even though the CDMA IS-95 system is already implemented in Simulink and is provided as a demo, there is no way of converting it into real Hardware. Using Xilinx System Generator we have made our implementation capable of being translated into any of the HDL codes. This can be then mapped onto appropriate FPGA easily. We have used the hardware co-simulation feature of the Xilinx System generator to create a library of the basic building blocks of the IS-95 system. This library can be used for implementing to create the various channels that are the part of the CDMA system.