Analysis of process variation's effect on SRAM's read stability (original) (raw)
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Analytical modeling of read stability metric of SRAM cell in nanoscale era
2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), 2010
In this paper, we propose an analytical model for read stability metric (read margin) of sub-45nm SRAM cells. First, analytical expressions for V read and V trip of the cell are derived. The expressions are obtained using a simple model for the I-V characteristics of the transistors valid for sub-45nm technologies. The I-V model, which is based on the n-th power model, has integer powers of voltage. The accuracy of the analytical model is verified by comparing its results with those of HSPICE simulations. The results show a very good accuracy for the proposed model for a wide range of transistor sizes. The accuracy of the models is also verified in the presence of threshold voltage fluctuations.
Read stability and Write ability analysis of different SRAM cell structures
2014
SRAM cell read stability and write-ability is major concerns in nanometer CMOS technologies, due to the progressive increase in intra-die variability and VDD scaling. This paper analyzes the read stability and write ability of 6T, 8T, 9T SRAM cell structures. SRAM cell stability analysis is typically based on Static Noise Margin (SNM) investigation. This paper represents the simulation of three SRAM cell topologies and their comparative analysis on the basis of read noise margin (RNM), write noise margin (WNM). Both 8T SRAM cell and 9T SRAM cell provides higher read noise margin as compared to 6T SRAM cell. Although the size of 9T SRAM cell is higher than that of the 8T SRAM cell but it provides higher write stability. In this paper we propose a methodology to characterize the DC noise margin of 6T, 8T and 9T SRAM. All simulations of the SRAM cell have been carried out in 130nm CMOS technology.
Static-Noise Margin Analysis during Read Operation of 6T SRAM Cells
SRAM cell stability analysis is typically based on Static Noise Margin (SNM) investigation when in hold mode, although many memory errors may occur during read operations. Given that SNM varies with each cell operation, a thorough analysis of SNM in read mode is required. In this paper we investigate the SRAM cell SNM during read operations analyzing various alternatives to improve cell stability in this mode. The techniques studied are based on transistor width, and word-and bit-line voltage modulations. We show that it is possible to improve cell stability during read operations while reducing current leakage, as opposed to current methods that improve cell read stability at the cost of leakage increase.
Microelectronics Reliability, 2012
This paper presents a technique for designing a variability aware SRAM cell. The architecture of the proposed cell is similar to the standard 6T SRAM cell with the exception that the access pass gates are replaced with full transmission gates. The paper studies the impact of V t (threshold voltage) variation on most of the design metrics of SRAM cell. The proposed design achieves 1.4Â narrower spread in I READ at the expense 1.2Â lower I READ at nominal V DD . It offers 1.3Â improvements in T RA (read access time) distribution at the expense of 1.2Â penalty in read delay. The proposed bitcell offers 1.1Â tighter spread in T WA (write access time) incurring 1.3Â longer write delay. It shows 180 mV of SNM (static noise margin) and is equally stable in hold mode. It offers 1.3Â higher RSNM (100 mV) compared to 6T (75 mV). It exhibits improved SINM (static current noise margin) distribution at the expense of 1.6Â lower WTI (write trip current). It offers 1.05Â narrower spread in standby power. Thus, comparative analysis based on Monte Carlo simulation exhibits that the proposed design is capable of mitigating impact of V t variation to a large extent.
Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies
IEEE Journal of Solid-State Circuits, 2006
SRAM cell read stability and write-ability are major concerns in nanometer CMOS technologies, due to the progressive increase in intra-die variability and scaling. This paper analyzes the read stability N-curve metrics and compares them with the commonly used static noise margin (SNM) metric defined by Seevinck. Additionally, new write-ability metrics derived from the same N-curve are introduced and compared with the traditional write-trip point definition. Analytical models of all these metrics are developed. It is demonstrated that the new metrics provide additional information in terms of current, which allows designing a more robust and stable cell. By taking into account this current information, scaling is no longer a limiting factor for the read stability of the cell. Finally, these metrics are used to investigate the impact of the intra-die variability on the stability of the cell by using a statistically-aware circuit optimization approach and the results are compared with the worst-case or corner-based design.
SRAM Cell Stability: A Dynamic Perspective
IEEE Journal of Solid-State Circuits, 2009
SRAM cell stability assessment is traditionally based on static criteria of data stability requiring three coincident points in DC butterfly curves. This definition is based on static (DC) characteristics of the cell transistors. We introduce the dynamic criteria of cell data stability knowing that the cell operates in a dynamic environment alternating between access and non-access conditions. The proposed definition of the dynamic data stability criteria introduces a new bound for the cell static noise margin (SNM). It reveals that the true noise margin of the cell can be made considerably higher than the conventional SNM once the cell access time is sufficiently shorter than the cell time-constant. This phenomena can be used to extend the noise margin in (partial) subthreshold SRAMs. Moreover, a simulation method for verification of the dynamic data stability criteria is presented. Silicon measurement results in 130 nm CMOS technology confirms the concept of dynamic data stability and designer's ability to trade timing and static parameters. Finally, it is shown that the long time constant due to the subthreshold operation of the cell can be exploited to maintain data stability with proper choice of access and recovery time.
In this paper we introduce Noise (the Static Noise present in 7T SRAM cell) effect the stability of cell. Actually SNM is present in SRAM cell which is effect the stability in read operation of the 7T SRAM cells. SRAM cell stability analysis is a based on Static Noise Margin (SNM) investigation when in read mode, although many memory errors may occur during read operations. So that SNM varies with each cell operation, a thorough analysis of SNM in read mode is required. In this paper we investigate the SRAM cell SNM during read operations analyzing various alternatives to improve cell stability in this mode. The techniques studied are based on transistor width, and word-and bit-line voltage modulations. We show that it is possible to improve cell stability during read operations while reducing word line voltage.
Stability Analysis of 6T SRAM at 32 Nm Technology
2020
ABSTRACT: SRAM area is expected to exceed 90% of overall chip area because of the demand for higher performance, lower power, and higher integration. To increase memory density, memory bitcells are scaled to reduce their area by 50% each technology node. High density SRAM bitcells use the smallest devices in a technology, making SRAM more vulnerable for variations. This variation effect the stability of SRAM. This paper investigates Static random access memory (SRAM) stability in hold/standby, read and write mode. In this paper different techniques to find Static Noise Margin (SNM), Read margin and write margin are discussed. The effect of supply voltage, transistor scaling, word line voltage, threshold voltage, and temperature on SRAM stability is analysis in Standby and Read Mode. From 0.7V to 1.2V the read stability increase 231% and Standby stability increase 135%. When the cell ratio changes from 1 to 3 the stability of SRAM during read mode gets doubled. This paper also invest...
Stability Analysis of SRAM on Trip Point
2018
Abstract: The most important property of an SRAM cell is its ability to hold data under varying conditions. This property is commonly referred to as the stability of the cell. In this paper we describe this property of SRAM. The data stability affects by the various parameters like supply voltage, cell ratios, threshold voltages, and static noise sources, etc. This paper investigates the concept of SRAM cell data stability from the traditional approaches like trial and error technique.
SRAM dynamic stability: Theory, variability and analysis
2008 IEEE/ACM International Conference on Computer-Aided Design, 2008
Technology scaling in sub-100nm regime has significantly shrunk the SRAM stability margins in data retention, read and write operations. Conventional static noise margins (SNMs) are unable to capture nonlinear cell dynamics and become inappropriate for state-of-the-art SRAMs with shrinking access time and/or advanced dynamic read-write-assist circuits. Using the insights gained from rigorous nonlinear system theory, we define the much needed SRAM dynamic noise margins (DNMs). The newly defined DNMs not only capture key SRAM nonlinear dynamical characteristics but also provide valuable design insights. Furthermore, we show how system theory can be exploited to develop CAD algorithms that can analyze SRAM dynamic stability characteristics three orders of magnitude faster than a brute-force approach while maintaining SPICE-level accuracy. We also demonstrate a parametric dynamic stability analysis approach suitable for low-probability cell failures, leading to three orders of magnitude runtime speedup for yield analysis under high-sigma parameter variations.