A DMT–based VDSL receiver front–end design in 0.35µm BiCMOS (original) (raw)

2002

Abstract

A VDSL receiver front-end with a programmable gain low noise amplifier is presented. The amplifier consumes only 35mW from a 3.3V supply in a 0.35µm BiCMOS technology and is suitable for DMT-based VDSL systems with bandwidths up to 12MHz. The linearity is expressed in Missing Band Depth (MBD) for a worst case bandplan. The LNA uses an inverting architecture and has a constant input impedance. A technique was used to suppress the distortion caused by the switches in the signal path. The area is only 0.2mm2.

Benan Bayrakci hasn't uploaded this paper.

Let Benan know you want this paper to be uploaded.

Ask for this paper to be uploaded.