Integrated optical interconnect for on-chip data transport (original) (raw)

Optical interconnect for on-chip data communication

2006

It is believed that the concept of integrated optical interconnect is a potential technological solution to alleviate some of the ever more pressing issues involved in exchanging data between cores in SoC architectures (inter-line crosstalk, latency, global throughput, connectivity and power consumption). This abstract summarises work carried out in the framework of the EU-funded PICMOS project on the quantitative comparison of optical interconnect to electrical interconnect in the context of on-chip data communication.

Electrical and Optical On-Chip Interconnects in Scaled Microprocessors

2005 IEEE International Symposium on Circuits and Systems, 2005

Interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to satisfy the design requirements of delay, power, bandwidth, and noise. Onchip optical interconnect is therefore being considered as a potential substitute for electrical interconnect. Based on predictions of optical device development, electrical and optical interconnects are compared for various design criteria. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect at the 22 nm technology node are approximately one tenth of the chip edge length.

Optical solutions for system-level interconnect

2004

Throughput, power consumption, signal integrity, pin count and routing complexity are all increasingly important interconnect issues that the system designer must deal with. Recent advances in integrated optical devices may deliver alternative interconnect solutions enabling drastically enhanced performance. This paper begins by outlining some of the more pressing issues in interconnect design, and goes on to describe system-level optical interconnect for inter-and intra-chip applications. Inter-chip optical interconnect, now a relatively mature technology, can enable greater connectivity for parallel computing for example through the use of optical I/O pads and wavelength division multiplexing. Intra-chip optical interconnect, technologically challenging and requiring new design methods, is presented through a proposal for heterogeneous integration of a photonic "above-IC" layer followed by a design methodology for on-chip optical links. Design technology issues are highlighted and the paper concludes with examples of the use of optical links in clock distribution (with quantitative comparisons of dissipated power between electrical and optical clock distribution networks) and for novel network on chip architectures.

Optical interconnects: out of the box forever

IEEE Journal of Selected Topics in Quantum Electronics, 2003

Based on a variety of optimization criteria, recent research has suggested that optical interconnects are a viable alternative to electrical interconnects for board-to-board, chip-to-chip, and on-chip applications. However, the design of modern high-performance computing systems must account for a variety of performance scaling factors that are not included in these analyses.

PERFORMANCE ENHANCEMENT OF MULTI-CORE PROCESSOR SYSTEMS ON-CHIP BY USING OPTICAL INTERCONNECTS

Multiprocessor system is growing and an attractive platform providing high performance, high energy efficiency with limited power and bandwidth. The Conventional electrical interconnects may not be fulfill the communication demand due to bandwidth density and energy consumption constraints. Optical interconnects with recent progress may be adopted due to its ultrahigh bandwidth, low latency and low energy consumption. The Optical interconnects include inter/ intra chip network, both are designed separately. Inter chip networks, exploiting the inherent properties of optical links. We place the chips far away from each other to reduce power density but still provide high performance, high energy efficiency. Inter chip network contain N data channel which are parallel to each other with the same design. Here all the core-clusters are interconnected with the parallel closed loop channel. The cluster access the channel with optical switching box. This approach utilize the advantages of optical interconnects in long distance communication. Optical interconnects dynamically partitions each data channel into multiple sections, each section improves the performance by designing the chip using optical interconnects. In this article, we propose a design to avoid the traffic and collision over network and also measure the losses of optical interconnects and save the energy upto 85% as well as improved throughput upto 90%.

Challenges for on-chip optical interconnects

Optoelectronic Integration on Silicon II, 2005

As integrated circuit interconnect dimensions continue to shrink and signaling frequencies increase, interconnect performance degrades. The performance degradation is due to several factors such as power consumption, cross-talk, and signal attenuation. On-chip optical interconnects are a potential solution to these scaling issues because they offer the promise of providing higher bandwidth. In this paper, progress on the major on-chip optical

On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions

IEEE Journal of Selected Topics in Quantum Electronics, 2000

Intrachip optical interconnects can outperform electrical wires but the required parameters for optical components are yet unknown. Here the ITRS is used as a reference point to derive the requirements that optical components must meet.

Predictions of CMOS compatible on-chip optical interconnect

Integration, the VLSI Journal, 2007

Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy these design requirements. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one-tenth of the chip edge length at the 22 nm technology node. r

An intra-chip free-space optical interconnect

ACM SIGARCH Computer Architecture News, 2010

Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless scaling, if uncompensated, degrades the performance and signal integrity of on-chip metal interconnects. These systems have therefore become increasingly communications-limited. The communications-centric nature of future high performance computing devices demands a fundamental change in intra- and inter-chip interconnect technologies. Optical interconnect

Optical Interconnects for Network on Chip

Nano-Networks and …, 2007

Abstract-This paper resumes some state-of-the-art results of research in view of the realization of optical interconnects as physical link for Network on Chip (NoC). Emphasis is given in particular to amorphous Silicon technology for its actual technological compatibility with CMOS ...