System on Wafer: A New Silicon Concept in SiP (original) (raw)
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Design and development of a multi-die embedded micro wafer level package
2008
The primary trend in electronics industry is product miniaturization. Both design and manufacturing engineers are looking for ways to make products lighter, smaller, less expensive, and at the same time faster, more powerful, reliable, user-friendly, and functional. A partial list of today's "shrinking" products would include cellular phones, personal and sub-notebook computers, pagers, PCMCIA cards, camcorders, palmtop organizers, telecommunications equipment, and automotive components. With silicon chips continue integrating more functionality as per Moore's Law, the packaging is challenged to integrate and shrink. Chips First or Embedded Chip packaging is a revolutionary way to overcome these recent packaging integration challenges. Packaging researchers have worked on embedded packaging and developed newer way of embedding the chip. The PBGA replaced the lead frame based peripheral array packages, in which the die is electrically connected to circuit board (PCB) substrate by wire bonding or flip chip technology, before covering with molding compound. Embedded Wafer level packaging takes the next step, eliminating the PCB, as well as the need to use wire bonding or flip-chip bumps to establish electrical connection. This paper deals with the development embedding multiple dies at wafer level.
Demonstration of a Heterogeneously Integrated System-on-Wafer (SoW) Assembly
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018
This paper describes the integration of a System-on-Wafer (SoW) assembly using test dielets mounted on a Silicon Interconnect Fabric (Si-IF) with an inter-dielet spacing of 100 μm and using 10 μm interconnect pitch. The continuity within and across the dielet assembly is shown using daisy chains of Au-capped Cu-Cu thermal compression bonds. The daisy chains run not only through every dielet but also across all the adjacently mounted dielets on the Si-IF. The interconnections exhibited an effective contact resistivity of 0.8-0.9 Ω-μm 2 and an average shear strength of 125 MPa. Our investigations showed that Argon plasma pre-treatment improves the shear strength of the metal bonds by a factor of 5X. Thermal simulation of the SoW assembly showed superior heat spreading across the assembly in a checkerboard configuration of alternate hot (0.5 W/mm 2) and cold (0.1 W/mm 2) dielets with an average temperature of 82 °C & 78 °C respectively.
Technology Requirements for Chip-On-Chip Packaging Solutions
Proceedings Electronic Components and Technology, 2005. ECTC '05., 2005
The trend towards smaller, lighter and thinner products requires a steady miniaturization which has brought-up the concept of Chip Scale Packaging (CSP). The next step to reduce packaging cost was the chip packaging directly on the wafer. Wafer Level Packaging (WLP) enables the FC assembly on PWB without interposers. New and improved microelectronic systems require significant more complex devices which could limit the performance due to the wiring of the subsystems on the board. 3-D packaging using the existing WLP infrastructure is one of the most promising approaches. Stacking of chips for chip-on-chip packages can be done by wafer-to-wafer stacking or by chip-to-wafer stacking which is preferable for yield and die size considerations. This chip-on-chip packaging requires a base die with redistribution traces to match the I/O layout of both dice. This allows the combination of the performance advantage of flip chip with the options of WLP. To avoid the flip chip bonding process the thin chip integration (TCI) concept can be used. Key elements of this approach are extremely thin ICs (down to 20 µm thickness) which are incorporated into the redistribution. This technology offers excellent electrical properties of the whole microelectronic system. The focus of this paper will be the technology requirements for the realization of different kinds of chip-onchip packages.
3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias
IEEE Journal of Solid-state Circuits, 2006
System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two-and three-dimensional silicon integration technologies are emerging which will likely support next-generation high-volume electronic applications and may serve high-performance computing applications. This paper will discuss a few emerging technologies which offer opportunities for enhanced circuit performance, or reduced power as one example.
Fan-Out Wafer-Level Packaging for Heterogeneous Integration
IEEE Transactions on Components, Packaging and Manufacturing Technology, 2018
The design, materials, process, fabrication, and reliability of a heterogeneous integration of four chips and four capacitors by a fan-out wafer-level packaging (FOWLP) method are investigated in this paper. Emphasis is placed on the application of a new assembly process for fabricating the redistribution layers of the FOWLP. Reliability assessments, such as the thermal cycling and drop test, are also performed.
Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12"/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm 2 panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.
MRS Proceedings, 2006
The very large development of home and domestic electronic appliances as well as portable device has led the microelectronics industry to evolve in two complimentary directions : “More Moore” with the continuous race towards extremely small dimensions hence the development of SoCs (System on Chip) and more recently a new direction that we could name “More than Moore” with the integration of devices that were laying outside the chips and here the creation of SiPs (System in Package).These two approaches are not in competition one with the other: the paper will show some examples of integrated nano systems that use several SoCs.The technology we have developed is called Silicon Based System in Package. The first products using this technology are now in volume production and used mainly in the field of wireless communications.This new technology relies on four pillars. Passive integration is the first. Very efficient and high quality factor capacitors and inductors have been integrate...
2011
Two embedded micro-wafer-level packages (EMWLP) with 1) laterally placed and 2) vertically stacked thin dies are designed and developed. Three-dimensional stacking of thin dies is demonstrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10 mm × 10 mm × 0.4 mm and solder ball pitch of 0.4 mm. As part of the development several key processes like thin die stacking, 8-in wafer encapsulation using compression molding, low-temperature dielectric with processing temperature less than 200°C have been developed. The EMWLP components success fully pass 1000 air to air thermal cycling (-40°C to 125°C), unbiased highly accelerated stress testing (HAST) and moisture sensitivity level (MSL3) tests. Developed EMWLP also show good board level TC (>; 1000 cycles) and drop test reliability results. Integration of thin film passives like inductors and capacitors are also demonstrated on EMWLP platform. Developed thin film passives show a higher Q-factor when compared to passives on high resistivity silicon platform. Thermo-mechanical simulation studies on developed EMWLP demonstrate that systemic control over die, RDL, and package thicknesses can lead to designs with improved mechanical reliability.