Iterative Decoding of Multiple-Step Majority Logic Decodable Codes (original) (raw)
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Iterative Threshold Decoding of One Step Majority Logic Decodable block Codes
2007 IEEE International Symposium on Signal Processing and Information Technology, 2007
Iterative threshold decoding of product and parallel concatenated block codes based on one step majority logic decodable (OSMLD) codes has proven to perform remarkably well on AWGN channels. For these codes to be applicable in wireless environment, their performance on fading channels must be examined. The purpose of this work is to study the performance of our iterative threshold decoding algorithm on the Rayleigh fading channel. Results have shown that the slope of the bit-error rate (BER) curve is as steep as for the Gaussian channel. We also present a comparison between our results and those for convolutional turbo code in terms of BER performance.
Iterative Threshold Decoding of Majority Logic Decodable Codes on Rayleigh Fading Channels
setit.rnu.tn
Iterative threshold decoding of product and parallel concatenated block codes based on one step majority logic decodable (OSMLD) codes has proven to perform remarkably well on AWGN channels. For these codes to be applicable in wireless environment, their performance on fading channels must be examined. The purpose of this work is to study the performance of our iterative threshold decoding algorithm on the Rayleigh fading channel. Results have shown that the slope of the bit-error rate (BER) curve is as steep as for the Gaussian channel. We also present a comparison between our results and those for convolutional turbo code in terms of BER performance.
IEEE Transactions on Communications, 2014
This paper presents two iterative decoding algorithms for a class of non-binary two-step majority-logic (NB-TS-MLG) decodable cyclic codes. A partial parallel decoding scheme is also introduced to provide a balanced trade-off between decoding speed and storage requirements. Unlike non-binary one-step MLG decodable cyclic codes, the Tanner graphs of which are 4-cycle-free, NB-TS-MLG decodable cyclic codes contain a large number of short cycles of length 4, which tend to degrade decoding performance. The proposed algorithms utilize the orthogonal structure of the parity-check matrices of the codes to resolve the degrading effects of the short cycles of length 4. Simulation results demonstrate that the NB-TS-MLG decodable cyclic codes decoded with the proposed algorithms offer coding gains as much as 2.5 dB over Reed-Solomon codes of the same lengths and rates decoded with either hard-decision or algebraic soft decision decoding. Index Terms-Extended min-sum algorithm, majority-logic decoding, non-binary LDPC codes, cyclic codes. I. INTRODUCTION F INITE geometry codes received considerable attention in the late 1960s and 1970s [1]-[3]. These codes form an important class of cyclic codes, which can be systematically encoded with linear shift registers and decoded with majoritylogic decoding (MLGD) [4]. Based on finite geometries, there are two types of cyclic codes: one-step and multi-step MLG decodable. One-step MLG decodable cyclic codes were rediscovered in 2001 [5] as finite geometry low-density paritycheck (FG-LDPC) codes with 4-cycle-free Tanner graphs [6]. Long FG-LDPC codes provide error correction performance approaching to Shannon's theoretical limit [7] when decoded using belief propagation algorithms, such as the sum-product algorithm [8] and the min-sum algorithm [9]. In contrast, numerous short cycles of length 4 involved in multi-step MLG decodable cyclic codes limit the effectiveness of the standard belief propagation algorithm [10]. Consequently, only a small amount of coding gain is achieved at a considerable increment in decoding complexity. Efforts to overcome this key disadvantage have led to the development of efficient iterative decoding
A New Iterative Threshold Decoding Algorithm for non-binary OSMLD Codes
2022 5th International Conference on Advanced Communication Technologies and Networking (CommNet)
The performance of iterative decoding algorithm for one-step majority logic decodable (OSMLD) codes is investigated. We introduce a new soft-in soft-out of APP threshold algorithm which is able to decode theses codes nearly as well as belief propagation (BP) algorithm. However the computation time of the proposed algorithm is very low. The developed algorithm can also be applied to product codes and parallel concatenated codes based on block codes. Numerical results on both AWGN and Rayleigh channels are provided. The performance of iterative decoding of parallel concatenated code (17633,8595) with rate 0.5 is only 1.8 dB away from the Shannon capacity limit at a BER of 10-5 .
Gradient-descent decoding of one-step majority-logic decodable codes
Physical Communication, 2020
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2013
In this paper we present a study of the impact of connection schemes on the performance of iterative decoding of Generalized Parallel Concatenated block (GPCB) constructed from one step majority logic decodable (OSMLD) codes and we propose a new connection scheme for decoding them. All iterative decoding connection schemes use a soft-input soft-output threshold decoding algorithm as a component decoder. Numerical result for GPCB codes transmitted over Additive White Gaussian Noise (AWGN) channel are provided. It will show that the proposed scheme is better than Hagenauer's scheme and Lucas's scheme [1] and slightly better than the Pyndiah's scheme.
Parallel Architecture for Iterative Decoder of Majority Logic Codes for High Data Rate Applications
2016
parallel architectures for majority logic decoder of low complexity for high data rate applications. These architectures are hard decision decoder architecture (Hard in- Hard out (HIHO)), the SIHO threshold decoding (Soft in – Hard out) and the SISO threshold decoding (Soft in – Soft out). The chosen code is the Difference Set Cyclic DSC code. The VHDL (Very high speed integrated circuit Hardware Description Language) design and the synthesis of such architectures show that such decoders can achieve high data rate with low complexity. In our case, the iterative decoder associated to the fully parallel SISO threshold decoders allows achieving high data rates, 2 clock cycles for two iterations with a complexity of 7350LEs.
2009
This paper presents two novel iterative reliability-based majority-logic algorithms for decoding LDPC codes. Both algorithms are binary message-passing algorithms and require only logical operations and integer additions. Consequently, they can be implemented with simple combinational logic circuits. They either outperform or perform just well as the existing weighted bit-flipping or other reliability-based decoding algorithms for LDPC codes in error performance
On Iterative Soft-Decision Decoding of Linear Binary Block Codes and Product Codes
IEEE Journal on Selected Areas in Communications, 1998
Iterative decoding methods have gained interest, initiated by the results of the so-called “turbo” codes. The theoretical description of this decoding, however, seems to be difficult. Therefore, we study the iterative decoding of block codes. First, we discuss the iterative decoding algorithms developed by Gallager (1962), Battail et al. (1979), and Hagenauer et al. (1996). Based on their results, we propose a decoding algorithm which only uses parity check vectors of minimum weight. We give the relation of this iterative decoding to one-step majority-logic decoding, and interpret it as gradient optimization. It is shown that the used parity check set defines the region where the iterative decoding decides on a particular codeword. We make plausible that, in almost all cases, the iterative decoding converges to a codeword after some iterations. We derive a computationally efficient implementation using the minimal trellis representing the used parity check set. Simulations illustrate that our algorithm gives results close to soft decision maximum likelihood (SDML) decoding for many code classes like BCH codes. Reed-Muller codes, quadratic residue codes, double circulant codes, and cyclic finite geometry codes. We also present simulation results for product codes and parallel concatenated codes based on block codes
Iterative Threshold Decoding Of High Rates Quasi-Cyclic OSMLD Codes
International Journal of Advanced Computer Science and Applications, 2016
Majority logic decoding (MLD) codes are very powerful thanks to the simplicity of the decoder. Nevertheless, to find constructive families of these codes has been recognized to be a hard job. Also, the majority of known MLD codes are cyclic which are limited in the range of the rates. In this paper a new adaptation of the Iterative threshold decoding algorithm is considered, for decoding Quasi-Cyclic One Step Majority logic codes (QC-OSMLD) codes of high rates. We present the construction of QC-OSMLD codes based on Singer difference sets of rate 1/2, and codes of high rates based on Steiner triple system which allows to have a large choice of codes with different lengths and rates. The performances of this algorithm for decoding these codes on both Additive White Gaussian Noise (AWGN) channel and Rayleigh fading channel, to check its applicability in wireless environment, is investigated.