MONTE-CARLO SIMULATION OF ULTRA-THIN FILM SILICON-ON-INSULATOR MOSFETs (original) (raw)
Related papers
Monte Carlo simulation of electron transport properties in extremely thin SOI MOSFET's
IEEE Transactions on Electron Devices, 1998
Electron mobility in extremely thin-film siliconon-insulator (SOI) MOSFET's has been simulated. A quantum mechanical calculation is implemented to evaluate the spatial and energy distribution of the electrons. Once the electron distribution is known, the effect of a drift electric field parallel to the Si-SiO 2 interfaces is considered. The Boltzmann transport equation is solved by the Monte Carlo method. The contribution of phonon, surface-roughness at both interfaces, and Coulomb scattering has been considered. The mobility decrease that appears experimentally in devices with a silicon film thickness under 20 nm is satisfactorily explained by an increase in phonon scattering as a consequence of the greater confinement of the electrons in the silicon film.
IEEE Transactions on Electron Devices, 2003
In this paper, we have extensively investigated the silicon thickness dependence of the low field electron mobility in ultrathin silicon-on-insulator (UT-SOI) MOSFETs operated both in single-and in double-gate mode. A physically based model including all the scattering mechanisms that are known to be most relevant in bulk MOSFETs has been extended and applied to SOI structures. A systematic comparison with the measurements shows that the experimental mobility dependence on the silicon thickness (SI) cannot be quantitatively explained within the transport picture that seems adequate for bulk transistors. In an attempt to improve the agreement with the experiments, we have critically rediscussed our model for the phonon scattering and developed a model for the scattering induced by the SI fluctuations. Our results suggest that the importance of the surface optical (SO) phonons could be significantly enhanced in UT-SOI MOSFETs with respect to bulk transistors. Furthermore, both the SO phonon and the SI fluctuation scattering are remarkably enhanced with reducing SI , so that they could help explain the experimental mobility behavior.
IEEE Transactions on Electron Devices, 2010
In this paper, together with the accompanying Part I, an easy-to-implement electron mobility model that accurately predicts low-field mobility in bulk MOSFETs and UTB-SOI FETs fabricated on different crystal orientations is developed. In Part I, the general features of the model have been presented. In this Part II, the effects induced by extremely small silicon thicknesses are addressed. These effects include the scattering induced by interface states and silicon thickness fluctuations, intervalley-phonon scattering suppression, and surface optical phonons. Besides, corrections necessary for double-gate FETs are considered. This allows the validity of the model presented in Part I to be extended to single-and double-gate FETs with silicon thicknesses as small as about 2.5 nm.
MONTE CARLO STUDY ON ELECTRON TRANSPORT PROPERTIES IN DOUBLE-GATE FULLY DEPLETED SOI-MOSFETs
The transport properties of very thin double gate SOI MOSFETs, have been studied. W e have shown the importance of volume inversion, which greatly reduces the dependence of the electron mobility on the surface scattering mechanisms, and enhances the mobility at high inversion charge concentrations. W e have also shown that if the silicon film is extremely thin, electron mobility abruptly decreases due to stronger phonon scattering.
IEEE Transactions on Electron Devices, 2007
A number of experiments have recently appeared in the literature that extensively investigate the silicon-thickness dependence of the low-field carrier mobility in ultrathin-body silicon-on-insulator (SOI) MOSFETs. The aim of this paper is to develop a compact model, suited for implementation in devicesimulation tools, which accurately predicts the low-field mobility in SOI single-and double-gate MOSFETs with Si thicknesses down to 2.48 nm. Such a model is still missing in the literature, despite its importance to predict the performance of present and future devices based on ultrathin silicon layers.
IEEE Transactions on Electron Devices, 2005
The ultimate limits in scaling of conventional MOSFET devices have led the researchers from all over the world to look for novel device concepts, such as ultrathin-body (UTB) silicon-on-insulator (SOI), dual-gate SOI devices, FinFETs, focused ion beam MOSFETs, etc. These novel devices suppress some of the short channel effects exhibited by conventional MOSFETs. However, a lot of the old issues still remain and new issues begin to appear. For example, in UTB SOI devices, dual-gate MOSFETs and in FinFET devices, quantum-mechanical size quantization effects significantly affect the overall device behavior. In addition, unintentional doping leads to considerable fluctuation in key device parameters. In this work we investigate the role of two-dimensional quantization effects in the operation of a narrow-width SOI device using an effective potential scheme in conjunction with a three-dimensional ensemble Monte Carlo particle-based device simulator. We also investigate the influence of unintentional doping on the operation of this device. We find that proper inclusion of quantization effects is needed to explain the experimentally observed width dependence of the threshold voltage. With regard to the problem of unintentional doping, impurities near the middle portion of the source end of the channel have most significant impact on the device drive current and the fluctuations in the device threshold voltage.
International Journal of Computer Applications, 2010
With the scaling of MOSFETs in to sub-100nm regim, Silicon on-Insulator (SOI), single gate (SG) and double gate (DG) MOSFETs are expected to replace tradional bulk MOSFETS. These novel MOSFETs devices will be strong contenders in RF applications in wireless communication market. This work is concerned about the device scaling and different design structures of nano scale SOI MOSFETs. The compression of SG and DG configuration and electrical performance demonstrates the superiority of DG-MOSFETs: Ideal sub threshold swing, input output Tran conductance and remarkably improved Tran conductance (higher than twice the value in SG-MOSFETs). The experimental data and the difference between SG and DG modes is explained, also the optimization of body thickness and doping profile are elaborated. The impact of energy quantization on gate tunneling current is studied for double and ultra thin body MOSFETs. Reduced vertical electrical field and quantum confinement in the channel of these thinbody devices causes a decrease in gate leakage. But all these are acceptable for channel length above 15 nm.
Simulation Of High Performance Nanoscale Partially Depleted Soi N-Mosfet Transistors
2017
Invention of transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key for the development of nanoelectronics technology. In the first part of this manuscript, we present a new generation of MOSFET transistors based on SOI (Silicon-On-Insulator) technology. It is a partially depleted Silicon-On-Insulator (PD SOI MOSFET) transistor simulated by using SILVACO software. This work was completed by the presentation of some results concerning the influence of parameters variation (channel length L and gate oxide thickness Tox) on our PDSOI n-MOSFET structure on its drain current and kink effect.
Quantum simulations of an ultrashort channel single-gated n-MOSFET on SOI
IEEE Transactions on Electron Devices, 2002
We present quantum mechanical simulations of a single-gated ultrashort channel MOSFET on silicon-on-insulator (SOI). Ballistic transport is assumed, in order to investigate ideal device performance. In particular, the electrical characteristics and the dependence on the SOI body thickness variation and doping of source and drain is elaborated. The results show that excellent performance can be achieved for devices with channel lengths down to 15 nm for a single-gated device layout. The influence of the SOI-film roughness is investigated with an SOI body thickness down to 2.5 nm. Extremely high transconductances far in excess of today's state-of-the-art devices can be expected if the doping level in source and drain is chosen appropriately. We give the relevant design rules for the fabrication of such devices.