TEL62: an integrated trigger and data acquisition board (original) (raw)
Related papers
The FPGA based Trigger and Data Acquisition system for the CERN NA62 experiment
Journal of Instrumentation, 2014
The main goal of the NA62 experiment at CERN is to measure the branching ratio of the ultra-rare K + → π + νν decay, collecting about 100 events to test the Standard Model of Particle Physics. Readout uniformity of sub-detectors, scalability, efficient online selection and lossless high rate readout are key issues. The TDCB and TEL62 boards are the common blocks of the NA62 TDAQ system. TDCBs measure hit times from sub-detectors, TEL62s process and store them in a buffer, extracting only those requested by the trigger system following the matching of trigger primitives produced inside TEL62s themselves. During the NA62 Technical Run at the end of 2012 the TALK board has been used as prototype version of the L0 Trigger Processor.
2014 19th IEEE-NPSS Real Time Conference, 2014
A Time to Digital Converter (TDC) based system, to be used for most sub-detectors in the high-flux rare-decay experiment NA62 at CERN SPS, was built as part of the NA62 fully digital Trigger and Data AcQuisition system (TDAQ), in which the TDC Board (TDCB) and a general-purpose motherboard (TEL62) will play a fundamental role. While TDCBs, housing four High Performance Time to Digital Converters (HPTDC), measure hit times from sub-detectors, the motherboard processes and stores them in a buffer, produces trigger primitives from different detectors and extracts only data related to the lowest trigger level decision, once this is taken on the basis of the trigger primitives themselves. The features of the TDCB board developed by the Pisa NA62 group are extensively discussed and performance data is presented in order to show its compliance with the experiment requirements.
2008 IEEE Nuclear Science Symposium Conference Record, 2008
The Electronic Systems Engineering Department of the Computing Division at the Fermi National Accelerator Laboratory has developed a data acquisition system flexible and powerful enough to meet the needs of a variety of high energy physics applications. The system described in this paper is called CAPTAN (Compact And Programmable daTa Acquisition Node) and its architecture and capabilities are presented in detail here. The three most important characteristics of this system are flexibility, versatility and scalability. These three main features are supported by key architectural features; a vertical bus that permits the user to stack multiple boards, a gigabit Ethernet link that permits high speed communications to the system and the core group of boards that provide specific capabilities for the system. In this paper, we describe the system architecture, give an overview of its capabilities and point out possible applications.
A 40 MHz-pipelined trigger for K0→2π0 decays for the CERN NA48 experiment
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 1998
A first level trigger system based on a 40 MHz digital pipeline has been developed for the CERN NA48 experiment, aiming at measuring CP violation in the K 0 ! 2 decays.
Performance of the NA62 trigger system
Journal of High Energy Physics
The NA62 experiment at CERN targets the measurement of the ultra-rare K+topi+nuoverlinenu{K}^{+}\to {\pi}^{+}\nu \overline{\nu}K+topi+nuoverlinenu K + → π + ν ν ¯ decay, and carries out a broad physics programme that includes probes for symmetry violations and searches for exotic particles. Data were collected in 2016–2018 using a multi-level trigger system, which is described highlighting performance studies based on 2018 data.
L0TP+: the Upgrade of the NA62 Level-0 Trigger Processor
2020
The L0TP+ initiative is aimed at the upgrade of the FPGA-based Level-0 Trigger Processor (L0TP) of the NA62 experiment at CERN for the post-LS2 data taking, which is expected to happen at 100% of design beam intensity, corresponding to about 3.3 × 1012 protons per pulse on the beryllium target used to produce the kaons beam. Although tests performed at the end of 2018 showed a substantial robustness of the L0TP system also at full beam intensity, there are several reasons to motivate such an upgrade: i) avoid FPGA platform obsolescence, ii) make room for improvements in the firmware design leveraging a more capable FPGA device, iii) add new functionalities, iv) support the 4 beam intensity increase foreseen in future experiment upgrades. We singled out the Xilinx Virtex UltraScale+ VCU118 development board as the ideal platform for the project. L0TP+ seamless integration into the current NA62 TDAQ system and exact matching of L0TP functionalities represent the main requirements and ...
A 130nm ASIC prototype for the NA62 Gigatracker readout
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 2011
One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27 mm  60 mm. While the maximum pixel size is fairly large, 300 mm  300 mm the system has to sustain a very high particle rate, 1.5 MHz/mm 2 , which corresponds to 800 MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150 ps (rms). Therefore the front-end ASIC should provide for each pixel a 200 ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130 nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Converter based TDC, both of them implemented on each pixel cell. The End of Column circuit containing only digital logic is responsible for the data readout from the pixel cell. The whole chip works with a system clock of 160 MHz and the digital logic is SEU protected by the use of Hamming codes. The detailed architecture of the ASIC prototype and test results are presented.