A black box method for stability analysis of arbitrary SRAM cell structures (original) (raw)
Related papers
Analytical Modeling of SRAM Dynamic Stability
2006 IEEE/ACM International Conference on Computer Aided Design, 2006
In this paper, for the first time, a theory for evaluating dynamic noise margins of SRAM cells is developed analytically. The results allow predicting the transient error susceptibility of an SRAM cell using a closed-form expression. The key innovation involves using the methods of nonlinear system theory in developing the model. It is shown that when a transient noise of given magnitude affects a sensitive node of a cell, the bi-stable, feedback-driven nature of the cell determines whether the noise will be suppressed or will evolve to eventually flip state. The specific formal and quantitative result is a closed-form expression that can be used to predict whether a cell flip will occur for a noise signal with specific characteristics, and for a given SRAM cell design. Experiments show excellent match between the analytical prediction and the SPICE simulation results.
SRAM dynamic stability: Theory, variability and analysis
2008 IEEE/ACM International Conference on Computer-Aided Design, 2008
Technology scaling in sub-100nm regime has significantly shrunk the SRAM stability margins in data retention, read and write operations. Conventional static noise margins (SNMs) are unable to capture nonlinear cell dynamics and become inappropriate for state-of-the-art SRAMs with shrinking access time and/or advanced dynamic read-write-assist circuits. Using the insights gained from rigorous nonlinear system theory, we define the much needed SRAM dynamic noise margins (DNMs). The newly defined DNMs not only capture key SRAM nonlinear dynamical characteristics but also provide valuable design insights. Furthermore, we show how system theory can be exploited to develop CAD algorithms that can analyze SRAM dynamic stability characteristics three orders of magnitude faster than a brute-force approach while maintaining SPICE-level accuracy. We also demonstrate a parametric dynamic stability analysis approach suitable for low-probability cell failures, leading to three orders of magnitude runtime speedup for yield analysis under high-sigma parameter variations.
SRAM Cell Stability: A Dynamic Perspective
IEEE Journal of Solid-State Circuits, 2009
SRAM cell stability assessment is traditionally based on static criteria of data stability requiring three coincident points in DC butterfly curves. This definition is based on static (DC) characteristics of the cell transistors. We introduce the dynamic criteria of cell data stability knowing that the cell operates in a dynamic environment alternating between access and non-access conditions. The proposed definition of the dynamic data stability criteria introduces a new bound for the cell static noise margin (SNM). It reveals that the true noise margin of the cell can be made considerably higher than the conventional SNM once the cell access time is sufficiently shorter than the cell time-constant. This phenomena can be used to extend the noise margin in (partial) subthreshold SRAMs. Moreover, a simulation method for verification of the dynamic data stability criteria is presented. Silicon measurement results in 130 nm CMOS technology confirms the concept of dynamic data stability and designer's ability to trade timing and static parameters. Finally, it is shown that the long time constant due to the subthreshold operation of the cell can be exploited to maintain data stability with proper choice of access and recovery time.
Static-Noise Margin Analysis during Read Operation of 6T SRAM Cells
SRAM cell stability analysis is typically based on Static Noise Margin (SNM) investigation when in hold mode, although many memory errors may occur during read operations. Given that SNM varies with each cell operation, a thorough analysis of SNM in read mode is required. In this paper we investigate the SRAM cell SNM during read operations analyzing various alternatives to improve cell stability in this mode. The techniques studied are based on transistor width, and word-and bit-line voltage modulations. We show that it is possible to improve cell stability during read operations while reducing current leakage, as opposed to current methods that improve cell read stability at the cost of leakage increase.
Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric
2011 Asian Test Symposium, 2011
Current nanometric IC processes need to assess the robustness of memories under any possible source of disturbance: process and mismatch variations, bulk noises, supply rings variations, temperature changes, aging and environmental aggressions such as RF or on-chip couplings. In the case of SRAM cells, the static immunity to such perturbations is well characterized by means of the Static Noise Margin (SNM) defined as the maximum applicable series voltage at the inputs which causes no change in the data retention nodes. In addition, a significant number of disturbance sources present a transient behavior which has to be taken in consideration. In this paper, a metric to evaluate the cell robustness in the presence of transient voltage signals is proposed. Sufficiently high energy noise signals will compel the cell to flip to a failure state. On the other hand, sufficiently low energy noise signals will not be able to flip the cell and the state will be preserved. The Dynamic Noise Margin (DNM) metric is defined as the minimum energy of the voltage pulses able to flip the cell. A case example of transient voltage noise pulses on a 6T SRAM cell using 45nm technology has been studied. Simulation results show the use of the proposed metric as an indicator of cell robustness in the presence of transient voltage noise.
Journal of Nanostructures, 2021
Nano scale statistical variability which arises from discreteness of charge and granularity of matter has become one of major concerns in digital design particularly in sub-50nm technology nodes. Device intrinsic parameters such as the threshold voltage and drive current will be influenced by random dopants, line edge roughness and gate grain granularity which in turn results in variation of SRAM cell performance. Therefore, providing an accurate statistical model is one of the key issues among SRAM design community. Since both 6T and 8T SRAMs are widely used in the industry as standard cells, this article analyzes sensitivity of static noise margin (SNM) in response to statistical variations in 6-and 8-transistor cells. The results show that though 8T cells need more transistors and thus consume more area on the wafer compared with 6T cells, they are more stable and thus are better candidates for variability aware design in future technology nodes.
Stability Analysis of 6T SRAM at 32 Nm Technology
2020
ABSTRACT: SRAM area is expected to exceed 90% of overall chip area because of the demand for higher performance, lower power, and higher integration. To increase memory density, memory bitcells are scaled to reduce their area by 50% each technology node. High density SRAM bitcells use the smallest devices in a technology, making SRAM more vulnerable for variations. This variation effect the stability of SRAM. This paper investigates Static random access memory (SRAM) stability in hold/standby, read and write mode. In this paper different techniques to find Static Noise Margin (SNM), Read margin and write margin are discussed. The effect of supply voltage, transistor scaling, word line voltage, threshold voltage, and temperature on SRAM stability is analysis in Standby and Read Mode. From 0.7V to 1.2V the read stability increase 231% and Standby stability increase 135%. When the cell ratio changes from 1 to 3 the stability of SRAM during read mode gets doubled. This paper also invest...
Static Noise Margin Analysis of Various SRAM Topologies
ijetch.org
In the present time, great emphasis has been given to the design of low-power and high performance memory circuits. As an SRAM is a critical component in both high-performance processors and hand-held portable devices. So the ever-increasing levels of on-chip integration of SRAM, offers serious design challenges in terms of power requirement and cell stability. There is a significant increase in the sub-threshold leakage due to its exponential relation to the threshold voltage, and gate leakage due to the reducing gate-oxide thickness. In order to minimize the leakage current, the supply voltage is reduced drastically which reduces the threshold voltage of the cell.This reduces the threshold voltage of the cell which results in reduction of the Static Noise Margin (SNM) of the cell and affect the data stability of the cell, seriously. In this work, the solutions for theses two problems, in the conventional 6T SRAM Cell has been explored.
Stability Comparison of 6T and 8T SRAM Cell
2017
In the modern world as the technology is improving, there is a strong demand to design the SRAM cell for High speed application, Mainly the SRAM cell speed is depending on their (SNM) static noise margin and this is the one of the main parameter to design a memory cell, the static noise margin is going to affect the read margin and write margin.the SNM plays a vital role in stability of SRAM Cell. The analysis of SRAM read/write margin is essential for high speed SRAMs the tool used for simulation purpose is IC Station by Mentor Graphics using 350nm technology compared with 180nm KEYWORD: SRAM, Read noise margin, write margin, Static noise margin, Cell Ratio, Pull up Ratio
6T CMOS SRAM Stability in Nanoelectronic Era: From Metrics to Built-in Monitoring
Complementary Metal Oxide Semiconductor, 2018
The digital technology in the nanoelectronic era is based on intensive data processing and battery-based devices. As a consequence, the need for larger and energy-efficient circuits with large embedded memories is growing rapidly in current system-on-chip (SoC). In this context, where embedded SRAM yield dominate the overall SoC yield, the memory sensitivity to process variation and aging effects has aggressively increased. In addition, long-term aging effects introduce extra variability reducing the failure-free period. Therefore, although stability metrics are used intensively in the circuit design phases, more accurate and non-invasive methodologies must be proposed to observe the stability metric for high reliability systems. This chapter reviews the most extended memory cell stability metrics and evaluates the feasibility of tracking SRAM cell reliability evolution implementing a detailed bit-cell stability characterization measurement. The memory performance degradation observ...