Experimental/numerical investigation of the physical mechanisms behind high-field degradation of power HFETs and their implications on device design (original) (raw)
2001 GaAs Reliability Workshop. Proceedings (IEEE Cat. No.01TH8602), 2001
Abstract
In a previous paper we showed how simple drift-diffusion simulations backed up the hypothesis of electron trapping at the device surface between gate and drain as a mechanism able to consistently explain all of the experimentally observed degradation modes following a high-field (hot carrier) stress. This paper expands on such previous findings by showing: (i) simulation results of HFETs with
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