Quantum Simulation Study of a New Carbon Nanotube Field-Effect Transistor With Electrically Induced Source/Drain Extension (original) (raw)
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Simulations of Carbon Nanotube Field Effect Transistors
… Journal of Electronic Engineering Research, ISSN
As the scaling of Si MOSFET approaches towards its limiting value, new alternatives are coming up to overcome these limitations. In this paper first we have reviewed carbon nanotube field effect transistor (CNTFET) and types of CNTFET. We have then studied the effect of channel length and chirality on the drain current for planer CNTFET. The I d~Vd curves for planer CNTFETs having different channel lengths and diameters are plotted. For the same, I d~Vd curves for different applied gate voltages are also plotted. We have then discussed the effect of diameter on the characteristic curves for a cylindrical CNTFET. Finally a brief comparison between the performance of Si-MOSFET and CNTFET is given.
Carbon Nanotube Field Effect Transistor Model
Advanced Nanoelectronics, 2018
An analytical model that captures the essence of physical processes in a CNTFET's is presented. The model covers seamlessly the whole range of transport from driftdiffusion to ballistic. It has been clarified that the intrinsic speed of CNT's is governed by the transit time of electrons. Although the transit time is more dependent on the saturation velocity than on the weak-field mobility, the feature of high-electron mobility is beneficial in the sense that the drift velocity is maintained always closer to the saturation velocity, at least on the drain end of the transistor where electric field is necessarily high and controls the saturation current. The results obtained are applied to the modeling of the current-voltage characteristic of a carbon nanotube field effect transistor. The channel-length modulation is shown to arise from drain velocity becoming closer to the ultimate saturation velocity as the drain voltage is increased.
Simulation of carbon nanotube field-effect devices
4th IEEE Conference on Nanotechnology, 2004., 2004
Ab initio quantum mechanical numerical simulations have been used to study electronic transport in nanoscale electronic devices. We have developed a new code based on self-consistent density-functional tight-binding @FTB) method and non-equilibrium GRen's function (NEGF) formalism. Using this approach, we investigate the coherent transport properties of a long semiconducting CNT when the source-drain current is modulated by a coaxial gate. Exact boundary conditions for the electrostatic potential in the coaxial gate geometry are taken into account solving in real space a 3D Poisson equation. Results stress the importance of a gwd electrostatic-design of the gate contact to obtain the Same field-effect modulation we have in conventional planar MOSFET.
—This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the channel region, the resistive source/drain (S/D), the Schottky-barrier resistance, and the parasitic gate capacitances. More than one nan-otube per device can be modeled. Compared to silicon technology, the CNFETs show much better device performance based on the intrinsic CV /I gate-delay metric (six times for nFET and 14 times for pFET) than the MOSFET device at the 32-nm node, even with device nonidealities. This large speed improvement is significantly degraded (by a factor of five to eight) by interconnect capacitance in a real circuit environment. We performed circuit-performance comparison with all the standard digital library cells between CMOS random logic and CNFET random logic with HSPICE simulation. Compared to CMOS circuits, the CNFET circuits with one to ten carbon nanotubes per device is about two to ten times faster, the energy consumption per cycle is about seven to two times lower, and the energy-delay product is about 15–20 times lower, considering the realistic layout pattern and the interconnect wiring capacitance. Index Terms—Analytical model, carbon nanotube (CNT), carbon-nanotube field-effect transistor (CNFET), compact model, performance benchmarking, screening effect, SPICE.
CARBON NANOTUBE FIELD-EFFECT TRANSISTORS
International Journal of High Speed Electronics and Systems, 2006
This paper discusses the device physics of carbon nanotube field-effect transistors (CNTFETs). After reviewing the status of device technology, we use results of our numerical simulations to discuss the physics of CNTFETs emphasizing the similarities and differences with traditional FETs. The discussion shows that our understanding of CNTFET device physics has matured to the point where experiments can be explained and device designs optimized. The paper concludes with some thoughts on challenges and opportunities for CNTFET electronics.
c World Scientic Publishing Company NOVEL STRUCTURES FOR CARBON NANOTUBE FIELD EFFECT TRANSISTORS
2007
A carbon nanotube eld eect transistor (CNTFET) has been studied based on the Schrodinger{Poisson formalism. To improve the saturation range in the output charac-teristics, new structures for CNTFETs are proposed. These structures are simulated and compared with the conventional structure. Simulations show that these structures have a wider output saturation range. With this, larger drain-source voltage (V ds) can be used, which results in higher output power. In the digital circuits, higher V ds increases noise immunity.
This paper discusses a comprehensive analytical study of electrical properties of sin-gle‐wall conventional carbon nanotube field‐effect transistor (CNTFET) devices of subthreshold swing (SS), transconductance (g m), and extension resistance. The analytical expressions for SS and g m have been derived based on channel modulated potential. In the study, it was observed that SS value of the CNTFET device is equal to 60 mV/decade, which is smaller than the conventional and double gate metal‐ oxide‐semiconductor field‐effect transistors. The subthreshold swing degrades at larger tube's diameter and gate‐source voltage due to increased source‐drain leakage current. Carbon nanotube field‐effect transistor devices achieve larger g m at large gate‐source voltage, which has a disadvantage of reducing the allowable voltage swing at the drain. The extension resistance of the device falls with diameter of the tube. The subthreshold swing (SS) is the important parameter to sustain the scaling of silicon transistor because leakage power is strongly influenced by SS of the device. Subthreshold swing value indicates the minimum gate‐source voltage (V gs) required to lower the subthreshold current by a factor of 10. Steep SS devices are of great interest due to demand of power and energy‐efficient digital circuits. As metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) scaled below 45 nm, the subthreshold leakage current becomes more significant due to short‐channel effects (SCEs), parameter variations, 1-3 and strong coupling between temperature and subthreshold leakage current. 4,5 The fundamental thermodynamic limit on the minimum operational voltage and switching energy of the conventional FETs is ideally 60 mV/decade at room temperature, but in practice , the gate oxide screens the gate fields and the coupling between the gate and channel is not perfect, which causes SS to be larger than the ideal value. 6-10 The carbon nanotube FET (CNTFET) is a promising candidate for future electron devices, and rapid progress in this field has made it possible to fabricate CNTFET‐based integrated circuits. In facts, CNTFET is the substitute of silicon MOS due to excellent control of SCEs 11-13 as well as physical and electrical properties. 14,15 Although the SS of the CNTFET device has been reported theoretically by researchers, 16-18 this parameter has not been discussed in detail compared with the other parameters. In nanotube junctions, the parasitic resistance (R P) is given as the sum of contact resistance (R C) and the extension resistance (R ext). The R ext contributes more in the R P than in the R C. Lower R ext improves the intrinsic performance of the device. 19 In the literature, less attention has been given on the study of R ext compared with R C. 20 In this paper, we studied the SS and R ext of CNTFET after using our previously derived drain current equation. 15 The SS is close to 60 mV/decade at room temperature in CNTFET device. We have also observed that the SS of the CNTFET device is
Novel Structures for Carbon Nanotube Field Effect Transistors
International Journal of Modern Physics B, 2009
A carbon nanotube field effect transistor (CNTFET) has been studied based on the Schrödinger–Poisson formalism. To improve the saturation range in the output characteristics, new structures for CNTFETs are proposed. These structures are simulated and compared with the conventional structure. Simulations show that these structures have a wider output saturation range. With this, larger drain-source voltage (Vds) can be used, which results in higher output power. In the digital circuits, higher Vds increases noise immunity.