Effects of interface roughness scattering on radio frequency performance of silicon nanowire transistors (original) (raw)
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Theoretical investigation of surface roughness scattering in silicon nanowire transistors
Applied Physics Letters, 2005
In this letter, we report a three-dimensional (3D) quantum mechanical simulation to investigate the effects of surface roughness scattering (SRS) on the device characteristics of Si nanowire transistors (SNWTs). We treat the microscopic structure of the Si/SiO 2 interface roughness directly by using a 3D finite element technique. The results show that 1) SRS reduces the electron density of states in the channel, which increases the SNWT threshold voltage, and 2) the SRS in SNWTs becomes more effective when more propagating modes are occupied, which implies that SRS is more important in planar metal-oxide-semiconductor field-effect-transistors with many transverse modes occupied than in small-diameter SNWTs with few modes conducting.
2004
In this work, we present a quantum mechanical approach for the simulation of Si/SiO 2 interface roughness scattering in silicon nanowire transistors (SNWTs). The simulation domain is discretized with a threedimensional (3D) finite element mesh, and the microscopic structure of the Si/SiO 2 interface roughness is directly implemented. The 3D Schrödinger equation with open boundary conditions is solved by the non-equilibrium Green's function method together with the coupled mode space approach. The 3D electrostatics in the device is rigorously treated by solving a 3D Poisson equation with the finite element method. Although we mainly focus on computational techniques in this paper, the physics of SRS in SNWTs and its impact on the device characteristics are also briefly discussed.
Three-Dimensional Real-Space Simulation of Surface Roughness in Silicon Nanowire FETs
IEEE Transactions on Electron Devices, 2000
We address the transport properties of narrow gateall-around Silicon nanowires in the presence of surface-roughness (SR) scattering at the Si/SiO 2 interface, considering nanowire transistors with a cross section of 3 × 3 nm 2 and gate length of 15 nm. We present transfer characteristics and effective-mobility calculations based on a full 3-D real-space self-consistent Poisson-Schrödinger solver within the nonequilibrium Green's function formalism. The effect of SR is included via a geometrical method consisting in a random realization of potential fluctuations described via an exponential autocorrelation law. The influence on transfer characteristics and on low-field mobility is evaluated by comparison with the clean case and for different values of the root mean square of potential fluctuations. The method allows us to exactly account for mode-mixing and subband fluctuations and to evaluate the effect of SR up to all orders of the interaction. We find that SR scattering is mainly responsible for positive thresholdvoltage shift in the low-field regime, whereas SR-limited mobility slowly depends on the linear charge density, showing the inefficiency of mode-mixing scattering mechanism for very narrow wires.
IEEE Transactions on Electron Devices, 2000
We study the effect of surface roughness (SR) at the Si/SiO 2 interfaces on transport properties of quasi 1-D and 2-D silicon nanodevices by comparing the electrical performances of nanowire (NW) and double-gate (DG) field-effect transistors. We address a full-quantum analysis based on the 3-D self-consistent solution of the Poisson-Schrödinger equation within the coupled mode-space nonequilibrium Green function (NEGF) formalism. The influence of SR scattering is also compared with phonon (PH) scattering addressed in the self-consistent Born approximation. We analyze transfer characteristics, current spectra, density of states, and low-field mobility of devices with different lateral size, showing that the dimensionality of the quasi 1-D and 2-D structures induces significant differences only for thin silicon thicknesses. Thin NWs are found more sensitive to the SR-induced variability of the threshold voltage with respect to the DG planar transistors.
Semiclassical transport in silicon nanowire FETs including surface roughness
Journal of Computational Electronics, 2008
In this paper we investigate the effect of surface roughness scattering on transport in silicon nanowire FETs using a deterministic Boltzmann equation solver previously developed by the authors. We first solve the coupled Schrödinger-Poisson equations to extract the subband profiles along the channel, and then address the transport problem. Some features of the low-field mobility as a function of the wire diameter and gate bias are discussed and the effect of surface roughness on the I–V characteristics is presented.
Full quantum treatment of surface roughness effects in Silicon nanowire and double gate FETs
Journal of Computational Electronics, 2009
We review recent results on the effect of surface roughness on the transport properties of ultra-short devices like Silicon nanowire and double-gate FETs. We use a full quantum treatment within the non equilibrium Green's function (NEGF) formalism which allows us to take into account quantum confinement, quantum phase interference, out-ofequilibrium, and quasi-ballistic transport and focus on transfer characteristics and low-field mobility.
Journal of Applied Physics, 2007
We present a theoretical study of electron mobility in cylindrical gated silicon nanowires at 300 K based on the Kubo-Greenwood formula and the self-consistent solution of the Schrödinger and Poisson equations. A rigorous surface roughness scattering model is derived, which takes into account the roughness-induced fluctuation of the subband wave function, of the electron charge, and of the interface polarization charge. Dielectric screening of the scattering potential is modeled within the random phase approximation, wherein a generalized dielectric function for a multi-subband quasi-one-dimensional electron gas system is derived accounting for the presence of the gate electrode and the mismatch of the dielectric constant between the semiconductor and gate insulator. A nonparabolic correction method is also presented, which is applied to the calculation of the density of states, the matrix element of the scattering potential, and the generalized Lindhard function. The Coulomb scattering due to the fixed interface charge and the intra-and intervalley phonon scattering are included in the mobility calculation in addition to the surface roughness scattering. Using these models, we study the low-field electron mobility and its dependence on the silicon body diameter, effective field, dielectric constant, and gate insulator thickness.
Size Dependence of Surface-Roughness-Limited Mobility in Silicon-Nanowire FETs
IEEE Transactions on Electron Devices, 2000
Lateral size effects on surface-roughness-limited mobility in silicon-nanowire FETs are analyzed by means of a fullquantum 3-D self-consistent simulation. A statistical analysis is carried out by considering different realizations of the potential roughness at the Si-SiO 2 interfaces. Nanowires with lateral section varying from 3 × 3 to 7 × 7 nm 2 are considered. Effective mobility is computed by evaluating the electron density in a reduced channel region to eliminate parasitic effects from contacts. It is found that transport in wires with the smallest section is dominated by scattering due to potential fluctuations, resulting in a larger standard deviation of the effective mobility, whereas it is dominated by transverse-mode coupling in wires with larger section, resulting in a stronger influence of surface roughness at high gate voltages.
Electronic Properties of Silicon Nanowires: Confined Phonons and Surface Roughness
2006 Sixth IEEE Conference on Nanotechnology, 2006
Electron mobility in narrow, rectangular silicon nanowires is calculated using a Schrödinger-Monte-Carlo-Poisson transport simulator. Mobility lowering due to the carrier scattering with confined phonons in narrow wires and the influence of surface roughness within Ando's model are investigated.