Modeling of low frequency noise in FD SOI MOSFETs (original) (raw)
Related papers
Microelectronic Engineering, 2011
In this paper, we present a new numerical model of the inversion charge power spectral density in FDSOI MOSFET devices with ultra thin body. Numerical simulation results are compared to those of the classical formulation and to experimental data. A good agreement of measurements is obtained with the proposed model. The results show that the noise behavior in FDSOI MOSFETs is strongly related to the front and buried oxides defects, even if the channel is located at the front interface. In other words, the classical formulation of the flat-band voltage power spectral density (PSD) overestimate the front oxide trap density and no more holds true in SOI MOSFETs LFN characterization.
Low-frequency noise behavior of n-channel UTBB FD-SOI MOSFETs
2013 22nd International Conference on Noise and Fluctuations (ICNF), 2013
The low-frequency noise (LFN) behavior of ultra thin body and buried oxide (UTBB) fully-depleted (FD) siliconon-insulator (SOI) n-channel MOSFETs has been explored, emphasizing on the contribution of the buried-oxide (BOX) and the Si-BOX interface to the total drain current noise level. In order to successfully distinguish the different noise sources, measurements under different front and back gate voltages were performed. The noise spectra for all bias conditions consist of both flicker and Lorentzian-type noise components. A fitting method was used to extract the parameters of the LFN. It is shown that the flicker noise follows the carrier number with correlated mobility fluctuations model at both interfaces and the Si/BOX interface contributes to the total LFN level, even without back gate bias voltage. The front and back gate voltage dependence of the Lorentzian time constants indicates a uniform distribution of generation-recombination (g-r) centers within the silicon film. In addition, when the Si/BOX interface is accumulated, interface traps at the front gate are activated due to higher front gate voltages, giving rise to a different type of g-r noise.
High-frequency noise in FDSOI MOSFETs: a Monte Carlo investigation
Noise in Devices and Circuits, 2003
In this work, we study the static, dynamic and noise characteristics of FDSOI MOSFET's by means of numerical simulations validated by comparison with experimental data. For this purpose, we use a 2D Ensemble Monte Carlo simulator, taking into account, in an appropriate manner, the physical topology of a fabricated 0.25 µm gate-length FDSOI transistor. Important effects appearing in real transistors, such as surface charges, contact resistances, impact ionization phenomena and extrinsic parasitics are included in the simulation. This allows to accurately reproduce the experimental behavior of static and dynamic parameters (output and transference characteristics, g m /I D ratio, capacitances, etc.). Moreover, due to the characteristics of our microscopic approach, results are explained by means of internal quantities such as concentration, velocity or energy of carriers. The results of the Monte Carlo simulations for the typical four noise parameters (NF min , R n , phase and module of Γ opt ) of the 0.25 µm FDSOI MOSFET also show an exceptional agreement with experimental data. Once the reliability of the simulator has been confirmed, a full study of the noise characteristics of the device (intrinsic noise sources, normalized α, β and C parameters, experimental noise figures of merit) is performed. Taking advantage of the possibilities of the Monte Carlo method as a pseudoexperimental approach, the influence on these noise characteristics of the variation of some geometry parameters (downscaling the gate length and thickness of the active layer) is evaluated an interpreted in terms of microscopic transport processes.
Low-Frequency Noise Sources in Advanced UTBB FD-SOI MOSFETs
IEEE Transactions on Electron Devices, 2000
The low-frequency noise (LFN) sources in ultrathin body (8.7 nm) and buried oxide (10 nm) fully depleted siliconon-insulator (UTBB FD-SOI) n-and p-channel MOSFETs are analyzed. Both flicker and Lorentzian-type noise were observed, showing a dependence on the channel dimensions and the front/back gate bias conditions. The flicker noise component can be described by the carrier number with correlated mobility fluctuations model considering contribution from both interfaces. The Lorentzian-type noise originates mainly from generationrecombination (g-r) traps in the Si film, uniformly distributed in thin layers next to the drain and source contacts, and in some cases from g-r traps located at the front Si/oxide interface.
Low frequency noise in multi-gate SOI CMOS devices
Solid-State Electronics, 2007
Low frequency noise in Fully Depleted and Double Gate SOI-MOSFETs has been studied and compared for different front and backgate voltages with special emphasis on the coupling effect. Taking into account the coupling effect as the only parameter affecting the noise level for different back-gate voltages in multi-gate devices explains very well the experimental results obtained for the Fully Depleted devices where the silicon film thickness is 15 nm. In the Double Gate devices where the silicon film is just 6 nm, the effect of the back-gate bias on the noise level is the opposite to that in the Fully Depleted ones. It has been shown that as the carriers are pushed away from the Si/SiO 2 interfaces, their reduced amount of tunneling in the oxide traps decreases the noise level. Simulations have also been carried out to give an overview of the effect of the film thickness on the noise level when the back-gate bias is changed.
Analysis of 1/f Noise in Fully Depleted n-channel Double Gate SOI MOSFET
2005
An analysis of the 1/f or flicker noise in FD n-channel Double Gate SOI MOSFET is proposed. In this paper, the variation of power spectral density (PSD) of the equivalent noise voltage and noise current with respect to frequency, channel length and gate-tosource voltage at various temperatures and exponent C(i.e 1/f c ) is reported. The temperature is varied 125 K from to room temperature. The variation of PSD with respect to channel length down to 0.1µm technology is considered. It is analyzed that 1/f noise in FD n-channel Double Gate SOI MOSFET is due to both carrierdensity fluctuations and mobility-fluctuations. But controversy still exits to its origin.
A microscopic interpretation of the RF noise performance of fabricated FDSOI MOSFETs
IEEE Transactions on Electron Devices, 2006
In this paper, a detailed research of the high-frequency noise sources and figures of merit (FOMs) of fabricated deep-submicrometer n-channel fully depleted silicon-on-insulator MOSFETs is carried out. Special care is given to reproduce the main topology parameters, together with the most relevant parasitic elements of real devices in order to accomplish an accurate and reliable simulation. The information provided by the Monte Carlo (MC) tool allows getting a physical insight of the relationship between internal quantities and the main noise sources inside the device; moreover, the spectral density of velocity fluctuations has been analyzed spatially in order to determine the local current noise source in the gradual channel and velocity overshoot sections of the effective channel. Together with the calculation of intrinsic noise sources, the MC simulator is able to reproduce the measurements for the main noise FOMs in the RF and microwave frequency ranges. Moreover, the whole simulation framework allows addressing the importance of parasitic elements in the final value of these FOMs.
Solid-State Electronics, 2004
Device simulation is applied to the comparison of the RF and noise performance of bulk and single-gate ultra-thin SOI MOSFETs, with gate length in the range 70-100 nm. The results of our analysis point out that for a 70 nm gate length, the AC performance of ultra-thin SOI devices are limited by the parasitic source and drain resistances. The analysis of noise in these MOS structures, show that they are affected by comparable drain thermal noise; on the contrary, differences between the bulk and the SOI MOSFETs exist in terms of induced gate thermal noise and shot noise associated to the gate leakage current.
Low-frequency 1/f noise model for short-channel LDD MOSFETs
Solid-State Electronics, 1998
AbstractÐIn this paper, we present a physics-based, and analytical above-threshold low frequency 1/f noise model for short-channel LDD MOSFETs operated both in the triode and pentode modes. We ®rst develop an I±V model for LDD MOSFETs. The model was based on the quasi-two-dimensional Poisson equation and is a charge control model, expressed as a function of inversion charge density. The channel-length modulation was solved by using the quasi 2D approach and which was incorporated into the drain current equation. The parasitic source/drain resistance, the mobility reduction due to the transverse ®eld, and the carrier velocity saturation have also been taken into consideration. Then the 1/f drain current noise model was developed on the basis of oxide-trap-induced carrier number and surface mobility¯uctuations. The I±V and 1/f noise models were successfully applied to submicron LDD nMOSFETs and a good agreement between the modeled and experimental data was obtained. #
IEEE Transactions on Electron Devices, 1995
The empirical relationship between the device transconductance and the input-referred noise spectral density observed on partially depleted SOI n-MOSFETs is examined for other types of devices. As is shown, buried-channel p-MOSFETs processed in the same 1 μm CMOS SOI technology show the same behavior. The exponential dependence is also observed for SDI n-MOSFETs fabricated in a 3 μm CMOS technology, strongly emphasizing the generality of the result. Furthermore, it is valid both in linear operation (weak and strong inversion) and in saturation. The physical back-ground of this correlation is further elaborated and a new relationship is derived for the noise in the subthreshold regime.