A 22-Gb/s PAM-4 Receiver in 90-nm CMOS SOI Technology (original) (raw)
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A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS
2012
To overcome the limited bandwidth of chip-to-chip and backplane communication channels at multi-Gb/s data-rates, high-speed I/O transceivers employ a combination of DFE in the RX and FFE in the TX, since these equalizers complement each other to provide an effective equalization solution. Using RX-side FFE instead of TX-side FFE can bring important advantages to the transceiver: it obviates any back-channel for coefficient adaptation and improves RX interoperability with different TXs. RX-FFE is also preferable to simple peaking amplifiers, since it enables greater flexibility in setting the pre-cursor and post-cursor coefficients. However, traditional RX-FFEs with analog delay lines are not area efficient and do not support a wide range of data-rates. This paper describes design techniques that enable the realization of a RX with 4-tap FFE and 5-tap DFE, having area and power efficiency comparable to DFE-only RXs.
A 64-Gb/s 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET
IEEE Journal of Solid-State Circuits, 2018
A 64-Gb/s 4-pulse-amplitude modulation (PAM) transceiver fabricated with a 16-nm fin field effect transistor (FinFET) technology is presented with a power consumption that scales with link loss. The transmitter (TX) includes a three-tap feed-forward equalizer (FFE) (one pre and one post) achieving a level separation mismatch ratio (RLM) of 99% and a random jitter (RJ) of 162-fs rms. The maximum swing is 1.1 V ppd at a power consumption of 89.7 mW including clock distribution from a 1.2-V supply, corresponding to 1.39 pJ/bit. The receiver analog front end (RX-AFE) consists of a half-rate (HR) sampling continuous-time linear equalizer (CTLE) and 6-bit flash (1-bit folding) analog-to-digital converter (ADC) capable of non-uniform quantization. The non-uniform thresholds are selected based on a greedy search approach which allows the RX to reduce power at low channel loss in a highly granular manner and achieves better bit error rate (BER) than a uniform quantizer. For a channel with −8.6-dB loss at Nyquist, ADC can be configured in 2-bit mode, achieving BER < 1e − 6 at an RX-AFE power consumption of 100 mW. For a −29.5-dB loss channel, the RX-AFE consumes 283.9 mW and achieves a BER < 1e − 4 in conjunction with a software digital equalizer. For a −13.5-dB loss channel, a greedy search is used to optimize the quantization threshold levels, achieving an order of magnitude improvement in BER compared to uniform quantization.
IEEE Transactions on Circuits and Systems I-regular Papers, 2019
This paper proposes an SST-CML-Hybrid (SCH) output driver, and its corresponding hybrid-path feed-forward equalization (FFE) scheme, to enhance the energy efficiency of a PAM-4 transmitter (TX). Specifically, the SCH driver features one SST branch + one CML branch to co-synthesize the PAM-4 data, reducing substantially the signaling power, switching power and equalization power. The PAM-4 TX further integrates a halfrate serializer with 4-bit 3-tap FFE, duty-cycle correction circuits and a T-coil output matching network. Prototyped in 28-nm CMOS, the PAM-4 TX achieves a broadband return loss <−10dB up to 50 GHz, and occupies a compact die area of 0.0345 mm 2. Operating at 40 Gb/s and at a 0.9-V supply, the TX dissipates 19.5 mW, of which 6.4 mW is due to the SCH driver. The corresponding energy efficiencies are 0.16 and 0.5 pJ/bit for the SCH driver and TX, respectively; both compare favorably with the prior art.
IEEE Journal of Solid-State Circuits, 2000
This paper presents a 16-Gb/s 45-nm SOI CMOS transceiver for multi-standard backplane applications. The receiver uses a 12-tap DFE with circuit refinements for supporting higher data rates. Both the receiver and the transmitter use dynamic adaptation to combat parameter drift due to changing supply voltage and temperature. A 3-tap FFE is included in the source-series-terminated driver. The combination of DFE and FFE permits error-free NRZ signaling at 16 Gb/s over channels exceeding 30 dB loss. The 8-port core with two PLLs is fully characterized for 16GFC and consumes 385 m W/link.
1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus
IEEE Journal of Solid-State Circuits, 2001
A 1.6 Gb/s/pin 4-pulse-amplitude-modulated (PAM) multidrop signaling system has been designed. The motivation for multi-PAM signaling is discussed. The system uses single-ended + reference current-mode signaling with three dc references for maximum bandwidth per pin. A testchip with six I/O pins was fabricated in 0.35-m CMOS and tested in a 28evaluation system using on-chip 2 10 pseudorandom bit sequence (PRBS) generator/checkers. Two different 4-PAM transmitter structures were designed and measured. A high-gain windowed integrating input receiver with wide common-mode range was designed in order to improve signal-to-noise ratio when operating with smaller 4-PAM input levels. Gray coding allowed a folded preamplifier architecture to be used in the LSB input receiver to minimize area and power. In-system margins are measured via system voltage and timing shmoos with a master communicating with two slave devices.
A 106-Gb/s PAM-4 Silicon Optical Receiver
IEEE Photonics Technology Letters, 2019
We present a 106-Gb/s four-level pulse-amplitude modulation (PAM-4) silicon optical receiver consisting of a lownoise fully differential transimpedance amplifier (TIA) wirebonded to a high-speed silicon photonic Ge photodiode (PD). A low-noise operation is achieved through a fully differential TIA architecture, combined with active on-chip biasing for the PD. To the best of our knowledge, this is the first integrated low-power optical receiver to report (sub-)KP4-FEC bit error ratios up to 53 GBd PAM-4 without any digital signal processing or equalization to compensate the receiver. An optical modulation amplitude sensitivity of −5 dBm at 53 GBd is obtained, while consuming 160 mW (1.51 pJ/b at 53 GBd). The receiver achieves the bestreported sensitivities from 32-up to 53-GBd PAM-4, at the lowest reported power consumption.
A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI
2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007
The quest for high data rates at low power consumption and area has renewed interest in the source-series terminated (SST) driver. While SST drivers may not necessarily boast better performance than their counterparts using CML output stages, their advantage lies in their potential for lower power operation [1] and their ability to cope with a large range of termination voltages, which makes them a prime candidate for multi-standard TX. Given the increasing challenge in achieving acceptable analog performance in advanced digital CMOS technologies, the SST driver principle is based entirely on digital switching devices that are optimized for high-speed operation and continue to scale with technology. In this paper, the architecture and design of key components of a half-rate SST TX is presented that implements a versatile, power-and area-efficient equalization and impedance-tuning scheme. Furthermore, it achieves low jitter and negligible duty-cycle distortion (DCD), thanks to a clock duty-cycle cleanup circuit.
A 16Gb/s 3.7mW/Gb/s 8-tap DFE receiver and baud rate CDR with 30kppm tracking bandwidth
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2013
A 16 Gb/s I/O link receiver fabricated in 22 nm CMOS SOI technology is presented. Attenuation and ISI of transmitted NRZ data across PCB channels are equalized with a CTLE feeding an 8-tap DFE. The first tap uses digital speculation and the following seven taps are realized by means of the switched-capacitor technique. Timing recovery and control are performed with a Mueller-Müller type-A baud-rate CDR. The architecture is halfrate and requires one phase rotator. In total, each slice has six comparators to recover data and timing information. The secondorder digital CDR operates at quarter-rate and features a low-latency implementation of the proportional path. At 16 Gb/s, 1 Vppd PRBS31 data transmitted without FFE equalization is recovered across a PCB channel with 34 dB attenuation at 8 GHz. The measured tracking bandwidth is 31 kppm (16 GHz ± 496 MHz), and an amplitude of 3 UIPP is tolerated at 1 MHz sinusoidal jitter. The sinusoidal jitter amplitude tolerance measured at 10 Gb/s is 0.4 UIPP at 10 MHz and remains above 0.2 UIPP up to 1 GHz with PRBS31 data recovered (BER < 10 ) across a PCB channel with 27 dB attenuation at 5 GHz. The power efficiency is 3.7 mW/Gb/s, including the full-rate clock receiver.