Full 3D Statistical Simulation of Line Edge Roughness in sub-100nm MOSFETs (original) (raw)
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nrn Il 10 nm 40nm poly " nm~S i 10 nrn / Si !.i-7nm tox >< 0 lsox=20 nm Si 50 nm NBU LK = \018cm·3 II. ApPROACH The approach we propo se require s the identification of the relevant quantities that translate process variability into variability of electrical parameters. It involves the following three steps: Template 32 nm Template 22 nm 10nm \0 Figure I : Template structures for the 32 nm UTB SOl MOS FET (left) and the 22 nm double-gat e MOSF ET (right). The device is symmetrical. Doping profiles for source and drain are described in fll). The effective oxide thickn ess t ox is 1.2 nm for the 32 nm temp late and 1.1 nm for the 22 nm template. 50
Analysis of Statistical Fluctuations due to Line Edge Roughness in sub-0.1μm MOSFETs
Simulation of Semiconductor Processes and Devices 2001, 2001
We present a full-3D statistical analysis of line edge roughness (LER) in sub-0.1 µm MOSFETs. The modelling approach for line edges and the parameters used in the analysis take into account the statistical nature of the roughness. The results indicate that intrinsic fluctuations in MOSFETs due to LER become comparable in size to random dopant effects and can seriously inhibit scaling below 50 nm.
IEEE Trans. Electron Devices, 2011
We propose an approach to evaluate the effect on the threshold-voltage dispersion of nanoscale metal-oxidesemiconductor field-effect transistors (MOSFETs) of line-edge roughness, surface roughness, and random dopant distribution. The methodology is fully based on parameter sensitivity analysis, performed by means of a limited number of technology computer-aided design simulations or analytical modeling. We apply it to different nanoscale transistor structures, i.e., bulk 45-nm n-channel, 32-nm ultrathin-body silicon-on-insulator, and 22-nm double-gate MOSFETs. In all cases, our approach is capable of reproducing with very good accuracy the results obtained through 3-D atomistic statistical simulations at a small computational cost. We believe that the proposed approach can be a powerful tool to understand the role of the main variability sources and to explore the device design parameter space.
2008
The threshold voltage (V th ) of a nanoscale transistor is severely affected by random dopant fluctuations and line-edge roughness. The analysis of these effects usually requires atomistic simulations that are too expensive in computation for statistical circuit design. In this work, we develop an efficient SPICE simulation method and statistical transistor model that accurately predict threshold variation as a function of dopant fluctuations and gate length change caused by sub-wavelength lithography and the gate etching process. By understanding the physical principles of atomistic simulations, we (a) identify the appropriate method to divide a non-uniform gate into slices in order to map those fluctuations into the device model; (b) extract the variation of V th from the strong-inversion region instead of the leakage current, benefiting from the linearity of the saturation current with respect to V th ; and (c) propose a compact model of V th variation that is scalable with gate size and the amount of dopant and gate length fluctuations. The proposed SPICE simulation method is fully validated against atomistic simulation results. Given the post-lithography gate geometry, this approach correctly models the variation of device output current in all operating regions. Based on the new results, we further project the amount of V th variation at advanced technology nodes, helping shed light on the challenges of future robust circuit design.
Discrete random dopant distribution effects in nanometer-scale MOSFETs
Microelectronics Reliability, 1998
In this paper, discrete random dopant distribution eects in nanometer-scale MOSFETs were studied using threedimensional, drift-diusion``atomistic'' simulations. Eects due to the random¯uctuation of the number of dopants in the MOSFET channel and the microscopic random distribution of dopant atoms in the MOSFET channel were investigated. Using a simpli®ed model for the threshold voltage¯uctuation due to dopant number¯uctuation, we examine the standard deviations of the threshold voltage that can be expected for a highly integrated chip.
nsti.org
Proper analytical physically based model to predict fluctuations in the threshold voltage due to a single interface trap at a random location along the channel in a typical sub-50 nm MOSFET is of utmost significance. This research summary compares the efficacy of the existing analytical model based on dopant number fluctuation estimation in the channel of a MOSFET when compared to 3D Ensemble Monte Carlo (EMC) device simulation model in the presence of a random interface trap in the channel between the source and drain regions. The gate length of the nMOSFET device being investigated is 45 nm and the effective channel length is 32 nm. We demonstrate, for the first time, the shortcomings of the analytical models in capturing the short range Coulomb force interactions when the interface trap is located near the source end of the channel.
IEEE Transactions on Nanotechnology, 2011
In this paper, we investigate the threshold voltage and ON-current fluctuations due to the presence of charged traps located in the middle portion of the channel when the trap is moved from the source end to the drain end of the channel in a 45-nm technology node device with an effective channel length of 35 nm. Our thorough investigations suggest that the threshold voltage fluctuation and its standard deviation are much larger than the ON-current fluctuation since in the ON-state screening effectively reduces the strength of the trap Coulomb potential, which is not the case in the OFF-state. We believe that this is a first study that simultaneously investigates the effects of random dopant and random telegraph noise fluctuations that utilizes particle-based device simulators that correctly account for the long-range and the short-range Coulomb interaction. Unique feature of the approach is the proper incorporation, in a self-consistent manner, of the short-range Coulomb interaction via the real-space molecular dynamics routine. Indeed, Vasileska has pioneered this technique back in 1996. We also find that studies that do not account for the short-range Coulomb interaction correctly miss important feature that the threshold voltage standard deviations are not independent upon the position of the trap in the channel but are strongly correlated with it when the trap is located in the middle section of the source end of the channel. This suggests that an approach that correctly accounts for the short-range Coulomb interaction is a must when modeling either random dopant or random trap fluctuations in both the threshold voltage and the ON-current.
Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs
IEEE Transactions on Electron Devices, 2003
Intrinsic parameter fluctuations introduced by discreteness of charge and matter will play an increasingly important role when semiconductor devices are scaled to decananometer and nanometer dimensions in next-generation integrated circuits and systems. In this paper, we review the analytical and the numerical simulation techniques used to study and predict such intrinsic parameters fluctuations. We consider random discrete dopants, trapped charges, atomic-scale interface roughness, and line edge roughness as sources of intrinsic parameter fluctuations. The presented theoretical approach based on Green's functions is restricted to the case of random discrete charges. The numerical simulation approaches based on the drift diffusion approximation with density gradient quantum corrections covers all of the listed sources of fluctuations. The results show that the intrinsic fluctuations in conventional MOSFETs, and later in double gate architectures, will reach levels that will affect the yield and the functionality of the next generation analog and digital circuits unless appropriate changes to the design are made. The future challenges that have to be addressed in order to improve the accuracy and the predictive power of the intrinsic fluctuation simulations are also discussed.
IEEE Transactions on Electron Devices, 2013
Investigations on device variability for three different emerging field-effect transistor (FET) technologies are performed to determine the statistical dependence or independence of line edge roughness (LER) and random dopant fluctuation (RDF) variability mechanisms. The device candidates include standard inversion-mode (IM) FinFETs, junctionless (JL) FinFETs, and tunnel FETs (TFETs) designed for sub-32-nm generations. Using technology computer-aided design simulations, extracted standard deviations in linear and saturation threshold voltages (V T,lin and V T,sat), ON-state current (I ON), OFF-state current (I OFF), subthreshold swing (SS), and draininduced barrier lowering (DIBL) are compared for the cases: 1) when LER and RDF are separately modeled during device simulations and assumed to combine in an uncorrelated fashion, and 2) when LER and RDF are simultaneously modeled in device simulations and no assumption is made about their interaction. After performing the comparisons for each FET technology, we find that LER and RDF cannot be considered independent for IM-FinFETs and TFETs, but can be for JL-FinFETs. The different outcomes are related to local versus distributed variability dependencies in each transistor type. Our conclusions reinforce the need for more comprehensive treatment of variability effects to provide accurate estimations of expected device variability in junction-based FETs.