Linking EUV lithography line edge roughness and 16nm NAND memory performance (original) (raw)
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Microelectronics Reliability, 2012
The only way to keep pace with Moore's Law is to use probabilistic computing for memory design. Probabilistic computing is 'unavoidable', especially when scaled memory dimensions go down to the levels where variability takes over. In order to print features below 20 nm, novel lithographies such as Extreme Ultra Violet (EUV) are required. However, transistor structures and memory arrays are strongly affected by pattern roughness caused by the randomness of such lithography, leading to variability induced data errors in the memory read-out. This paper demonstrates a probabilistic-holistic look at how to handle bit errors of NAND Flash memory and trades-off between lithography processes and error-correcting codes to ensure the data integrity.
Microelectronics Reliability, 2011
The main reliability issue of highly scaled floating gate NAND Flash memories is the cross-cell interference phenomenon. This is an active area of research in microelectronics engineering. In the last decade, there has been much progress and there are already proposed models for extraction of parasitic capacitive couplings within floating gate transistors. However, most of simulation-based methodologies for evaluation of the impact of cross-cell interference on the electrical behavior rely on deterministic capacitive coupling, neglecting the variability effects. This approach ignores the variable nature of the capacitive couplings caused by technological limitations such as line edge roughness (LER) in advanced technological nodes. The aim of this work is to present an alternative approach of modeling threshold voltage disturbance propagation in a raw NAND Flash memory array, sourced by variability-affected parasitic capacitive couplings. The major contribution of this work is the introduction of probabilistic framework to link the process technology and system level.
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The capacitive coupling interference within floatinggate transistors is the main scaling barrier for highly dense NAND Flash memories. In this case study, we propose a simulation-based methodology for the variability modeling, which is caused by line edge roughness in advanced technological nodes. The aim of this work is to present the approach by modeling the threshold voltage disturbance propagation mechanism in a raw memory array, caused by the variability-affected parasitic coupling. The variability aware model is statistically designed for evaluation of the cell-to-cell interference variability impact on disturbances of threshold voltage and the error generation in a 16-nm half-pitch NAND Flash memory.
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Understanding how lithographic material and processing, affect linewidth roughness (LWR), and finally device operation is of immense importance in future scaled MOS transistors. The goal of this work is to determine the impact of LWR on device operation and to connect material and process parameters with it. To this end, we examine the effects of photoresist polymer length and acid diffusion length on LWR and transistor performance. Through the application of a homemade simulator of the lithographic process, it is shown that photoresists with small polymer chains and small acid diffusion lengths form lines with low LWR and thus lead to transistors with more reliable electrical performance.
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Due to projections of high scalability, Phase-Change Memory (PCM) is seen as a new main memory for computer systems. In fact, PCM may even replace DRAM, whose scaling limitations require new lithography technologies that are still unknown. On the down-side, PCM has low endurance when compared with DRAM, i.e., on average, a PCM cell can only withstand 10 8 bit-flips (modification of stored bit values) before the cell fails. To address PCM's low endurance, Error Correction Techniques (ECTs) have been proposed, which aim at increasing PCM's lifetime. However, previous lifetime analyses of ECTs have not considered the difference between the bit-flip frequencies of data bits and code bits (used to correct errors in data bits). That observation is crucial for the correct analysis of the ECTs since high bit-flip frequencies lead to faster wear-out.
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Emerging Lithographic Technologies XII, 2008
Line edge roughness (LER) and line width roughness (LWR) have raised questions and concerns as current lithography techniques reduce critical dimensions (CD) below 50 nm. There are few applications of controlled variation of LER and LWR, even among those which use electron beam direct writing (EBDW), although it is highly desirable to test the influence of systematical variation of LER and LWR on actual semiconductor devices. To get a clear understanding how and what the LERs and LWRs are influencing in EBDW, we have designed and fabricated transistor gates with programmed LER and LWR using EBDW and observed those based on CD-SEM metrology. The obtained results including calculated power spectrum density (PSD) shows the capability of EBDW to control the LER/LWR. Further, the influence of edge/width roughness in EBDW on device characteristics is reviewed and it gives how the effect of LWR/LER translates to device performance in DRAM process flow. It is found that the control of LWR is more important than that of LER for future lithography developments.
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In new-generation Flash memories, issues such as disturbs and data retention become more and more critical as a consequence of reduced cell size and decreased oxide thickness. Furthermore, the progressive increase in the cell count within a single die tends to decrease device reliability. In particular, reliability issues turn out to be more critical in multilevel (ML) Flash memories, due to the reduced spacing between adjacent programmed levels. It is therefore deemed that the use of on-chip error correction codes (ECCs) will gain widespread acceptance in large-capacity Flash memories. ECCs for Flash memories must have very fast and compact encoding/decoding circuitry so as to have a minimum impact on memory access time. The area penalty due to check cells must also be minimized. Moreover, specific codes must be developed for ML storage.
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A Bias-Dependent Model for the Impact of Process Variations on the SRAM Soft Error Immunity
IEEE Transactions on Very Large Scale Integration Systems, 2011
Nanometer SRAM cells are more susceptible to the particle strike soft errors and the increased statistical process variations, in advanced nanometer CMOS technologies. In this paper, an analytical model for the critical charge variations accounting for both die-to-die (D2D) and within-die (WID) variations, over a wide range of bias conditions, is proposed. The derived model is verified and compared to Monte Carlo simulations by using industrial hardware-calibrated 65-nm CMOS technology. This paper shows the impact of the coupling capacitor, one of the most common soft error mitigation techniques, on the critical charge variability. It demonstrates that the adoption of the coupling capacitor reduces the critical charge variability. The derived analytical model accounts for the impact of the supply voltage, from 0.1 to 1.2 V, on the critical charge and its variability.
Metrology, Inspection, and Process Control for Microlithography XXIII, 2009
The continues transistors scaling efforts, for smaller devices, similar (or larger) drive current/um and faster devices, increase the challenge to predict and to control the transistor off-state current. Typically, electrical simulators like SPICE, are using the design intent (as-drawn GDS data). At more sophisticated cases, the simulators are fed with the pattern after lithography and etch process simulations. As the importance of electrical simulation accuracy is increasing and leakage is becoming more dominant, there is a need to feed these simulators, with more accurate information extracted from physical on-silicon transistors. Our methodology to predict changes in device performances due to systematic lithography and etch effects was used in this paper. In general, the methodology consists on using the OPCCmax TM for systematic Edge-Contour-Extraction (ECE) from transistors, taking along the manufacturing and includes any image distortions like line-end shortening, corner rounding and line-edge roughness. These measurements are used for SPICE modeling. Possible application of this new metrology is to provide a-head of time, physical and electrical statistical data improving time to market. In this work, we applied our methodology to analyze a small and large array's of 2.14um2 6T-SRAM, manufactured using Tower Standard Logic for General Purposes Platform. 4 out of the 6 transistors used "U-Shape AA", known to have higher variability. The predicted electrical performances of the transistors drive current and leakage current, in terms of nominal values and variability are presented. We also used the methodology to analyze an entire SRAM Block array. Study of an isolation leakage and variability are presented.