NBTI-aware power gating for concurrent leakage and aging optimization (original) (raw)
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Power-gating: More than leakage savings
2010
While CMOS technology keeps running towards the physical limit of "nanometer" lengths, many critical design issues have already appeared in today's technologies (65nm and 45nm). Among them, Power and Reliability are the most insidious, because they affect energy efficiency and lifetime of digital systems. In this work we establish an important link between these two metrics. More specifically, we show how the most widely adopted leakage-reduction technique, that is power-gating, can go beyond its specific goal (i.e., saving leakage) by providing, per se, an effective solution to mitigate NBTI-induced aging. Based on this important property, we first present an automated methodology that allows a pushbutton estimation of the aging effects induced by NBTI on logic circuits (in terms of delay degradation) and SRAM memory cells (in terms of Static Noise Margin (SNM) reduction). Second, using an industrial 45nm technology, we quantify the actual capability of power-gating to further reduce the aging of CMOS devices and extend the lifetime of digital circuits.
Applicability of power-gating strategies for aging mitigation of CMOS logic paths
2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS), 2014
Aggressive CMOS technology scaling trends exacerbate the aging-related degradation of propagation delay and energy efficiency in nanoscale designs. Recently, Powergating has been utilized as an effective low-power design technique which has also been shown to alleviate some aging impacts. However, the use of MOSFETs to realize power-gated designs will also encounter aging-induced degradations in the sleep transistors themselves which necessitates the exploration of design strategies to utilize power-gating effectively to mitigate aging. In particular, Bias Temperature Instability (BTI) which occurs during activation of power-gated voltage islands is investigated with respect to the placement of the sleep transistor in the header or footer as well as the impact of ungated input transitions on interfacial trapping.
Device to Circuit Framework for Activity- Dependent NBTI Aging in Digital Circuits
IEEE Transactions on Electron Devices
A framework is proposed for activitydependent timing degradation due to p-FET negative bias temperature instability (NBTI) in digital circuits. A fixed-time compact model is proposed for NBTI and validated with physical model predictions for various digital circuits under different input signal slew and fan-out load conditions. The model is used to predict the timing degradation in digital circuits under arbitrary input activities. An equivalent degradation level is found that can be applied to all p-FETs in the circuit and can serve as an upper bound of degradation due to arbitrary input activity and avoid the conservative worst case dc analysis. The activity dependence is studied in microprocessors as well as arithmetic circuits under different actual workloads. Index Terms-Arbitrary input activity, compact model, digital circuits, frequency degradation, negative bias temperature instability (NBTI). I. INTRODUCTION N EGATIVE bias temperature instability (NBTI) continues to remain as a serious reliability concern in high-K metal gate p-FinFETs [1]-[5]. NBTI is due to the buildup of positive gate insulator charges, which shifts parameters such as threshold voltage (V T), transconductance (g m), and drain current (I D) with time [6], and affects circuit performance [7]-[15]. It results in higher timing delay (τ) in digital blocks, which leads to an increase in combinational Manuscript
Aging effects of leakage optimizations for caches
Besides static power consumption, sub-90nm devices have to account for NBTI effects, which are one of the major concerns about system reliability. Some of the factors that regulate power consumption also impact NBTI-induced aging effects; however, to which extent traditional low-power techniques can mitigate NBTI issues has not been investigated thoroughly. This is especially true for cache memories, which are the target of this work. We show how leakage optimization techniques can also be leveraged to extend the lifetime a cache. Experimental analysis points out that, while achieving a total energy reduction up to 80%, managing static power can also provide a 5x factor on lifetime extension.
Proceedings of the Design Automation & Test in Europe Conference, 2006
Negative Bias Temperature Instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. In this paper, we analyze the temporal delay degradation of logic circuits due to NBTI. We show that knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We also propose a sizing algorithm taking NBTI-affected performance degradation into account to ensure the reliability of nanoscale circuits for a given period of time. Experimental results on several benchmark circuits show that with an average of 8.7% increase in area one can ensure reliable performance of circuits for 10 years.
Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08, 2008
The effects of temperature on delay depend on several parameters, such as cell size, load, supply voltage, and threshold voltage. In particular, variations in V th can yield a temperature inversion effect causing a decreases of cell delay as temperature increases. This phenomenon, besides affecting timing analysis of a design, has important and unforeseeable consequences on power optimization techniques. In this paper, we focus on the impact of such effects on multi-V t design; in particular, we show how traditional dual-V t optimization may yield timing errors in circuits by ignoring temperature effects. Moreover, we present a temperature-aware dual-Vt optimization technique that reduces leakage power and can guarantee that the circuit is timing feasible at the boundary temperatures provided by the technology library. Our experiments show an average 27% leakage reduction with respect to a non temperature-aware design flow.
Modeling and mitigating NBTI in nanoscale circuits
2011 IEEE 17th International On-Line Testing Symposium, 2011
As semiconductor manufacturing has entered into nanoscale era, performance degradation due to Negative Bias Temperature Instability (NBTI) became one of the major threats to circuits reliability. In this paper, we present an NBTI gate delay model and a technique to mitigate its impact on circuit delays. First, we model NBTI impact on a gate while considering both the degradation of its own transistors and that of transistors in the adjacent gates. Simulation of our model on some ISCAS-85 benchmark circuits reveal that NBTI can cause up to 19.00% additional delay to a gate due to its own transistors degradation and up to 4.80% delay due to transistors degradation in adjacent gates after 10 years operation, resulting in a total delay of 23.80%. Therefore, we propose a transistor sizing techniques that not only mitigates NBTI induced delay of the gate under consideration but also minimizes its impact on the adjacent gates. Preliminary results of the mitigation technique applied to ISACAS-85 benchmark circuits show that with an average of 12% area overhead, the circuit delay will not exceed 15% after 10 years operation (i.e.; the introduced sizing technique realizes a delay reduction of about 45% as compared to the original circuit).
Leakage and variation aware thermal management of nanometer scale ICs
2004
For sub-100 nm CMOS technologies, leakage power forms a significant component of the total power dissipation, especially due to within-die and die-to-die variations in process (P), temperature (T) and supply voltage (V). Since leakage power and operating temperature are electrothermally coupled to each other, increasing power dissipation and thermal problems are becoming key concerns not only from a thermal management point of view but also because most reliability mechanisms are highly temperature sensitive. This paper provides an overview of a novel methodology for making temperature and reliability aware power/performance/cooling-cost tradeoffs in leakage dominant nanometer scale high-performance ICs. First, a framework to accurately estimate subthreshold leakage under both within-die and die-to-die parameter variations is outlined. It is shown that die-to-die temperature variations can significantly increase leakage power, mainly because of electrothermal couplings between power and temperature. Next, a recently developed self-consistent electrothermal methodology to accurately estimate the junction temperature is presented and is shown to be significant for thermal management of leakage and variation dominant CMOS technologies. The methodology is then applied to provide a reliability and thermally aware design space that can be used to optimize and compare various designs.
Impact of negative bias temperature instability on digital circuit reliability
Microelectronics Reliability, 2005
We have examined the impact of NBTI degradation on digital circuits through the stressing of ring oscillator circuits. By subjecting the circuit to pMOS NBTI stress, we have unambiguously determined the circuit reliability impact of NBTI. We demonstrate that the relative frequency degradation of the NBTI stressed ring oscillator increases as the voltage at operation decreases. This behavior can be explained by reduced transistor gate overdrive and reduced voltage headroom at the circuit level. We present evidence that donor interface state generation during NBTI stress is a significant component of the transistor degradation. Further, we show that the static noise margin of a SRAM memory cell is degraded by NBTI and the relative degradation increases as the operating voltage decreases.
Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011
Negative bias temperature instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent introduction of Hf-based high-k dielectrics for gate leakage reduction, positive bias temperature instability (PBTI), the dual effect in NMOS transistors, has also reached significant levels. Consequently, designs are required to build in substantial guardbands in order to guarantee reliable operation over the lifetime of a chip, and these involve large area and power overheads. In this paper, we begin by proposing the use of adaptive body bias (ABB) and adaptive supply voltage (ASV) to maintain optimal performance of an aged circuit, and demonstrate its advantages over a guardbanding technique such as synthesis. We then present a hybrid approach, utilizing the merits of both ABB and synthesis, to ensure that the resultant circuit meets the performance constraints over its lifetime, and has a minimal area and power overhead, as compared with a nominally designed circuit.