The Foundations of the EKV MOS Transistor Charge-Based Model (original) (raw)
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Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model
Solid-state Electronics, 2003
In this paper, the implications of inversion charge linearization in compact MOS transistor modeling are discussed. The charge-sheet model provides the basic relation among inversion charge and applied potentials, via the implicit surface potential. A rigorous derivation of simpler relations among inversion charge and applied external potentials is provided, using the technique of inversion charge linearization versus surface potential. The new concept of the pinch-off surface potential and a new definition of the inversion charge linearization factor are introduced. In particular, we show that the EKV charge-based model can be considered as an approximation to the more general approach presented here. An improvement to the EKV charge-based model is proposed in the form of a more accurate charge-voltage relationship. This model is analyzed in detail and shows an excellent agreement with the charge sheet model. The normalization of voltages, current and charges, as motivated by the inversion charge linearization, results in a major simplification in compact modeling in static as well as non-quasi-static derivations.
International Journal of Advanced Computer Science and Applications, 2016
In this paper, the EKV3.0 model used for RF analog designs was validated in all-inversion regions under bias conditions and geometrical effects. A conversion of empirical data of 180nm CMOS process to EKV model was proposed. A MATLAB developed algorithm for parameter extraction was set up to evaluate the basic EKV model parameters. Respecting the substrate, and as long as the source and drain voltages remain constant, the DC currents and g m /I D real transistors ratio can be reconstructed by means of the EKV model with acceptable accuracy even with short channel devices. The results verify that the model takes into account the second order effects such as DIBL and CLM. The sizing of the elementary amplifier was considered in the studied example. The sizing procedure based on g m /I D methodology was described considering a semi-empirical model and an EKV model. The two gave close results.
The EKV MOSFET Model for Circuit Simulation
1998
Physics-based modelling of weak, moderate and strong inversion. Relation with geometrical and process variables as: oxide thickness, junction depth effective channel length and width Effects of substrate doping level, substrate effect. Vertical field dependent mobility.
A compact non-quasi-static extension of a charge-based MOS model
IEEE Transactions on Electron Devices, 2001
This paper presents a new and simple compact model for the intrinsic metal oxide semiconductor (MOS) transistor, which accurately takes into account the non quasistatic (NQS) effects. This is done without any additional assumption or simplification than those required in the derivation of the classical description of the MOS channel charge. Moreover, the model is valid from weak to strong inversion and nonsaturation to saturation.
Accurate MOS modelling for analog circuit simulation using the EKV model
1996
Effective, manufacture-oriented design and simulation of high-performance analog and mixed-mode integrated circuits and systems is known to critically depend on the quality of extracted device parameters as well as the simulation model being used. This has gained increased relevance for low-voltage low-current designs, either in bulk CMOS or emerging SO1 technologies. The EKV model is introduced within a complete, statistically efficient and simple characterisation methodology. Valuable insight into the behavior of transistors in strong, moderate and weak inversion is gained, which also allows for increased design creativity. Measured results from a submicron bulk CMOS and a fully depleted SO1 process illustrate the accuracy of the EKV model and the associated parameter extraction under several geometries and regions of device operation.
This paper presents a novel, simple, single-piece MOSFET model, suitable for submicron and deep submicron technologies. The model is based on existing techniques (mainly on the interpolation scheme used in the initial version of the EKV model) and is capable of modeling both the drain current and the parasitic capacitances of the device, based on a quasi-static approach, in all regions of channel inversion. The major submicron effects taken into account are the velocity saturation, mobility degradation and output conductance effects. The main advantage of the proposed model is its simplicity and despite the fact that it uses only a small number of parameters, it provides accuracy that is comparable to more advanced and complex models such as BSIM. The proposed model can be used for first order analysis during the design of both analog and digital circuits, and has already been applied in the distortion analysis of analog and RF circuits.
IEEE Transactions on Nuclear Science, 2003
Design requirements for high-density front-end detectors and other high performance analog systems routinely force designers to operate devices in moderate inversion. However CMOS models have traditionally not handled this operating region very well. In this work the BSIM3V3 and EKV MOSFET models are evaluated in terms of their ability to model low voltage analog circuits. Simulation results for a standard 0.5um CMOS process are presented and compared to measured data. The data presented includes simulated and measured output conductance and transconductance efficiency for devices with channel lengths ranging from 0.5um to 33um. In addition the models are compared in terms of their ability to handle the different operating regions of the MOS transistor (weak, moderate, and strong inversion). The results highlight the difficulty of obtaining a model that accurately predicts the operation of high performance analog systems.
IEEE Transactions on Nuclear Science, 2003
Design requirements for high-density front-end detectors and other high performance analog systems routinely force designers to operate devices in moderate inversion. However CMOS models have traditionally not handled this operating region very well. In this work the BSIM3V3 and EKV MOSFET models are evaluated in terms of their ability to model low voltage analog circuits. Simulation results for a standard 0.5um CMOS process are presented and compared to measured data. The data presented includes simulated and measured output conductance and transconductance efficiency for devices with channel lengths ranging from 0.5um to 33um. In addition the models are compared in terms of their ability to handle the different operating regions of the MOS transistor (weak, moderate, and strong inversion). The results highlight the difficulty of obtaining a model that accurately predicts the operation of high performance analog systems.
Mosfet Simulation Using Matlab Implementation of the Ekv Model
The paper presents an implementation of EKV MOST model in Matlab environment. Parameter extraction and fitting procedures are briefly sketched.Open source modules for transistor characteristics and additional functions for parameter extraction and fitting are included in a Matlab toolbox. Model parameters are user defined to provide flexibility of design process.The accuracy of simulation results is ensured by using Labert's W interpolation function in the single expression for the drain current. Validation against conventional BSIM3v3 model for a 0.35 μm CMOS technology is performed.