Elevated field insulator (ELFIN) process for device isolation of ultrathin SOI MOSFETs with top silicon film less than 20 nm (original) (raw)
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IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONICS, COMMUNICATION & RENEWABLE ENERGY organized by the Amal Jyothi College of Engineering Erumely Rd, Kanjirappally, Koovappally, Kottayam, Kerala, 686518, 2013
This Paper elucidate the development of SOI-MOSFET using different gates like single, double, triple and gate all around structures. It is the Si MOSFET that is the fundamental device in the development very high density Integrated Circuits. Thus SOI Technology is used for reducing the Parasitic Capacitances. Improvement in the electrostatic control by gate of the channel is done with the increase in effective number of gates. It minimizes short-channel effect which arises due to the lines of electric field from source and drain affecting control of the channel region. The technologies like Double-gate (top and bottom gate) SOI MOSFET and the Gate-all-Around (GAA) helps to suppress various short channel effects like Drain-Induced Barrier Lowering (DIBL) and degradation in Sub-threshold slope. Nano MOSFETs are now the requirements of nano electronics and it is the Gate- all-Around MOSFET which is employed in silicon Nano wires.
Reduction of the reverse short channel effect in thick SOI MOSFET's
IEEE Electron Device Letters, 2000
We show that the reverse short channel effect (RSCE) is reduced in NMOS devices made in thick silicon-oninsulator (SOI) material. The reduction of the RSCE depends on the thickness of the Si overlayer. It is found that the thinner the Si film, the less the threshold voltage roll-on. The experimental findings are explained by a decrease of the lateral distribution of silicon interstitials generated at the source and drain (S/D) region and are related with their high recombination velocity at the buried oxide. This method can be used to separately test the influence of S/D point defects on the RSCE from other different hypotheses reported in the literature. Coupled process-device simulation reveals that the method is very sensitive to fundamental point defect properties.
IEEE Transactions on Electron Devices, 1998
The characteristics of reoxidized MESA isolation for silicon-on-insulator (SOI) MOSFET have been studied in terms of the dependence of device performance on silicon film thickness and channel width scaling. For devices with silicon film thickness (T T T Si ) smaller than a critical thickness, humps appear in subthreshold IV and negative threshold voltage shift is observed in narrow width devices. The width encroachment (1W W W ) also increases rapidly with reducing T T T Si . These observations can be explained by the formation of sharp beak and accelerated sidewall oxide growth in these devices. A simple guideline is given to optimize the reoxidation process for different T T T Si .
An anomalous device degradation of SOI narrow width devices caused by STI edge influence
IEEE Transactions on Electron Devices, 2002
The effects of shallow trench isolation (STI) on silicon-on-insulator (SOI) devices are investigated for various device sizes with three different gate shapes. Both NMOSFETs and PMOSFETs with the channel region butted to the STI show the reduction of mobility (NMOSFETs and PMOSFETs) and the increase of low-frequency noise as the channel width is reduced. In comparison, the devices without the STI-butted channel region show much less variation in mobility for various channel width. The degradation of MOSFETs' yield in SOI MOSFETs with the STI is found to be dependent on the device width since the contribution of the interface roughness (or damage) between the STI and the channel formed during the dry etch process becomes significant with the decrease of channel width and the increase of channel length. From the charge-pumping results, the interface state () generated by the STI process was identified as the cause of the anomalous degradation.
Characterization of ultrathin SOI film and application to short channel MOSFETs
…, 2008
In this study, a very dilute solution (NH 4 OH:H 2 O 2 :H 2 O 1:8:64 mixture) was employed to reduce the thickness of commercially available SOI wafers down to 3 nm. The etch rate is precisely controlled at 0.11Å s −1 based on the self-limited etching speed of the solution. The thickness uniformity of the thin film, evaluated by spectroscopic ellipsometry and by high-resolution x-ray reflectivity, remains constant through the thinning process. Moreover, the film roughness, analyzed by atomic force microscopy, slightly improves during the thinning process. The residual stress in the thin film is much smaller than that obtained by sacrificial oxidation. Mobility, measured by means of a bridge-type Hall bar on 15 nm film, is not significantly reduced compared to the value of bulk silicon. Finally, the thinned SOI wafers were used to fabricate Schottky-barrier metal-oxide-semiconductor field-effect transistors with a gate length down to 30 nm, featuring state-of-the-art current drive performance.
Comparison of electrical characteristics between Bulk MOSFET and Silicon-on-insulator (SOI) MOSFET
— Conventional MOSFET has already passed lower than 45nm transistor fabrication. As silicon is now hitting the atomic resolution and reaching its physical and electrical limitation, producing a proper working transistor tends to be more difficult and complicated. The major challenge is to fabricate a transistor with a nominal threshold voltage (V TH), lower gate leakage current (I OFF) and lower drain induced barrier lowering (DIBL). To overcome these problems, Silicon-on-insulator (SOI) MOSFET has been proposed, and it is believed to be capable of suppressing short channel effects (SCEs) by burying oxide layer in the silicon substrate. ATHENA and ATLAS module of SILVACO software were used in simulating the virtual fabrication and electrical performance of the transistors. An investigation on the characteristics and performance of the devices has been conducted in order to compare their electrical characteristics. The MOSFET structure was constructed by utilizing SILVACO Athena module, and the electrical characteristics were simulated using SILVACO Atlas module. The results of both the conventional bulk MOSFET and the SOI MOSFET were analyzed. It was observed that SOI MOSFET was superior compared to the conventional MOSFET in terms of their overall electrical characteristics.
Impact of Lateral Asymmetric Channel Doping on 45-nm-Technology N-Type SOI MOSFETs
IEEE Transactions on Electron Devices, 2000
Lateral asymmetric channel doping is applied to 45-nm technology NFET devices. The measured effective draincurrent enhancement over coprocessed symmetric control devices is 10%. Analysis reveals that the dominant physical mechanism, which accounts for two-third of the total enhanced drain current, is an 8% increase in the source-side injection velocity. The remaining one-third is attributed to the decreased drain-induced barrier lowering. This paper concludes with an analysis of the switching characteristics of CMOS inverters composed of an asymmetric NFET and a companion symmetric PFET and shows a 5% improvement in the delay. The improvement is explained in terms of the increased velocity and 30% reduction in drain junction capacitance.
Ultra-thin Si directly on insulator (SDOI) MOSFETs at 20 nm gate length
2014 International Conference on High Performance Computing and Applications (ICHPCA), 2014
This paper investigates on the scaling capability of nanoscale ultra-thin (UT) silicon directly on insulator (SDOI) single gate (SG) and double-gate (DG) Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs). An experiment is done by numerical modelling for both NMOS and PMOS by using device simulator TCAD Sentaurus. Based on the model, we conduct an investigation on Short Channel Effects (SCEs) like drain induced barrier lowering (DIBL), threshold voltage (Vth) shifting between two devices. Two types (Single and Double gate) enhancement type MOSFET has been studied for nanoscale CMOS digital application.