Semiconductor nanowire devices (original) (raw)
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Special Issue on Nanowire Transistors: Modeling, Device Design, and Technology
IEEE Transactions on Electron Devices, 2008
and UCLA are aimed at spintronics for low-power applications. He was also the Founding Director of the Nanoelectronics Research Facility, UCLA (established in 1989), with the infrastructure to further research in nanotechnology. He was the inventor of the strained layer MOSFET, quantum SRAM cell, and band-aligned superlattices. He is the author or coauthor of more than 300 papers published in international journals and conference proceeding. His research activities include semiconductor nanodevices and nanotechnology; self-assembly growth of quantum structures and cooperative assembly of quantum-dot arrays Sibased molecular beam epitaxy, quantum structures and devices; nanoepitaxy of heterostructures; spintronic materials and devices; and SiGe MBE and quantum structures. He is the holder of 17 patents. Dr. Wang serves on the editorial board of the Encyclopedia of Nanoscience and Nanotechnology
Enhanced Electrostatics for Low-Voltage Operations in Nanocrystal Based Nanotube/Nanowire Memories
IEEE Transactions On Nanotechnology, 2007
The metal nanocrystal (NC)/carbon nanotube (CNT) based nonvolatile memory has been proposed recently in comparison to the microfabricated Si channel and Si NCs in ultranarrow channel structure. The electrostatics of metal NC-CNT devices during memory operations differ significantly from the metal NC memory with planar silicon channel. In this paper, we present the theoretical analysis on the three-dimensional (3-D) electrostatics of the NC-CNT device during memory operations, to illustrate the experimentally observed large number of charge storage at low gate bias (5 V) despite a 100-nm-thick bottom-gate control dielectric. NCs are electrostatically more strongly coupled to the two-dimensional (2-D) gate electrode than to the one-dimensional (1-D) channel, even when the NCs are in much closer proximity to the 1-D channel, for efficient tunneling and low-voltage program operation. Under the retention condition, the NC-CNT devices have lower electric field across tunneling oxide than that in the case of a 2-D channel. This increasing electric field difference with respect to program versus retention operations indicates larger ratio between program and retention times. Together with the large number of electrons stored per NC, this enhanced electrostatics can be utilized either to reduce the operating voltage or to reduce statistical fluctuation of the information storage. Index Terms-Carbon nanotube (CNT), electrically erasable programmable read-only memory (EEPROM), electrostatics, field effect transistor, nanocrystal (NC), nonvolatile memories.
Vertically Integrated Nanowire-Based Unified Memory
Nano letters, 2016
A vertically integrated nanowire-based device for multifunctional unified memory that combine dynamic random access memory (DRAM) and flash memory in a single transistor is demonstrated for the first time. The device utilizes a gate-all-around (GAA) structure that completely surrounds the nanowire; the structure is built on a bulk silicon wafer. A vertically integrated unified memory (VIUM) device composed of five-story channels was fabricated via the one-route all-dry etching process (ORADEP) with reliable reproducibility, stiction-free stability, and high uniformity. In each DRAM and flash memory operation, the five-story VIUM showed a remarkably enhanced sensing current drivability compared with one-story unified memory (UM) characteristics. In addition to each independent memory mode, the switching endurance of the VIUM was evaluated in the unified mode, which alternatively activates two memory modes, resulting in an even higher sensing memory window than that of the UM. In addi...
Scaling of Nanowire Transistors
IEEE Transactions on Electron Devices, 2008
This paper considers the scaling of nanowire transistors to 10-nm gate lengths and below. The 2-D scale length theory for a cylindrical surrounding-gate MOSFET is reviewed first, yielding a general guideline between the gate length and the nanowire size for acceptable short-channel effects. Quantum confinement of electrons in the nanowire is discussed next. It gives rise to a ground-state energy and, therefore, a threshold voltage dependent on the radius of the nanowire. The scaling limit of nanowire transistors hinges on how precise the nanowire size can be controlled. The performance limit of a nanowire transistor is then assessed by applying a ballistic current model. Key issues such as the density of states of the nanowire material are discussed. Comparisons are made between the model results and the published experimental data of nanowire devices.
Core−Shell Heterostructured Phase Change Nanowire Multistate Memory
Nano Letters, 2008
Phase-change memory, which switches reversibly between crystalline and amorphous phases, is promising for next generation data-storage devices. In this work, we present a novel, nonbinary data-storage device using core-shell nanowires to significantly enhance memory capacity by combining two phase-change materials with different electronic and thermal properties to engineer different onsets of amorphous-crystalline transitions. Electric-field induced sequential amorphous-crystalline transition in core-shell nanowires displays three distinct electronic states with high, low, and intermediate resistances, assigned as data "0", "1", and "2".
TEM investigations of gate-all-around nanowire devices
Semiconductor Science and Technology, 2019
Vertically stacked gate-all-around nanowires (GAA NWs) are considered a promising architecture for ultimately scaled complementary metal oxide semiconductor devices. These are the natural evolution of the fin-shaped field effect transistor (finFET) design and enable a better electrostatic control and a higher drive current per footprint w.r.t. previous architectures. Transmission electron microscopy (TEM) analysis is employed in the development stages of these devices to investigate morphology, material diffusion, oxidation and strain in order to achieve the desired nanowires shape and size and the required performances. Nano beam diffraction and geometric phase analysis of high-resolution scanning TEM (STEM) images are used in this work to evaluate strain at the nmscale along the nanowires at different steps of the fabrication process. Initially strained Ge layers, in the early stages of the GAA NWs fabrication, relax after the fin-reveal and source/drain etching process steps. Strain is then restored after source/drain epitaxial deposition and maintained till the NWs release. TEM analyses of these structures are particularly challenging due to the dimensions of the GAA NWs which are smaller than the thickness of a typical TEM specimen. This generates artifacts due to different materials and multiple structures overlapping in projection in TEM images. To avoid these issues, several TEM lamellae at different positions in the device and/or 3D imaging STEM/energy dispersive spectroscopy tomography are employed.
Over the past decade extensive studies of single semiconductor nanowire and nanowire array photovoltaic devices have explored the potential of these materials as platforms for a new generation of efficient and cost-effective solar cells. This feature review discusses strategies for implementation of semiconductor nanowires in solar energy applications, including advances in complex nanowire synthesis and characterization, fundamental insights from characterization of devices, utilization and control of the unique optical properties of nanowires, and new strategies for assembly and scaling of nanowires into diverse arrays that serve as a new paradigm for advanced solar cells.
Facile Integration of Ordered Nanowires in Functional Devices
The integration of one dimensional (1D) nanostructures of non-industry-standard semiconductors in functional devices following bottom-up approaches is still an open challenge that hampers the exploitation of all their potential. Here, we present a simple approach to integrate metal oxide nanowires in electronic devices based on controlled dielectrophoretic positioning together with proof of concept devices that corroborate their functionality. The method is flexible enough to manipulate nanowires of different sizes and compositions exclusively using macroscopic solution-based techniques in conventional electrode designs. Our results show that fully functional devices, which display all the advantages of single-nanowire gas sensors, photodetectors, and even field-effect transistors, are thus obtained right after a direct assembly step without subsequent metallization processing. This paves the way to low cost, high throughput manufacturing of general-purpose electronic devices based on non-conventional and high quality 1D nanostructures driving up many options for high performance and new low energy consumption devices.
Observation of diameter dependent carrier distribution in nanowire-based transistors
Nanotechnology, 2011
The successful implementation of nanowire (NW) based field-effect transistors (FET) critically depends on quantitative information about the carrier distribution inside such devices. Therefore, we have developed a method based on high-vacuum scanning spreading resistance microscopy (HV-SSRM) which allows two-dimensional (2D) quantitative carrier profiling of fully integrated silicon NW-based tunnel-FETs (TFETs) with 2 nm spatial resolution. The key elements of our characterization procedure are optimized NW cleaving and polishing steps, the use of in-house fabricated ultra-sharp diamond tips, measurements in high vacuum and a dedicated quantification procedure accounting for the Schottky-like tip-sample contact affected by surface states. In the case of the implanted TFET source regions we find a strong NW diameter dependence of conformality, junction abruptness and gate overlap, quantitatively in agreement with process simulations. In contrast, the arsenic doped drain regions reveal an unexpected NW diameter dependent dopant deactivation. The observed lower drain doping for smaller diameters is reflected in the device characteristics by lower TFET off-currents, as measured experimentally and confirmed by device simulations.
Size-dependent phase transition memory switching behavior and low writing currents in GeTe nanowires
Applied Physics Letters, 2006
Synthesis and device characteristics of highly scalable GeTe nanowire-based phase transition memory are reported. The authors have demonstrated reversible phase transition memory switching behavior in GeTe nanowires, and obtained critical device parameters, such as write and erase currents, threshold voltage, and programming curves. The diameter dependence of memory switching behavior in GeTe nanowires was studied and a systematic reduction of writing currents with decreasing diameter was observed, with currents as low as 0.42 mA for a 28 nm nanowire. Results show that nanowires are very promising for scalable memory applications and for studying size-dependent phase transition mechanisms at the nanoscale. Disciplines Engineering | Materials Science and Engineering Comments