Design of a programmable CMOS Charge-Pump for phase-locked loop synthesizers (original) (raw)
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Design and Analysis of Low Power CMOS Charge Pump Circuits For Phase-Locked Loop
2015
A new high efficiency charge pump circuit is designed and realized in 130nm CMOS process. This paper work analyses the design of various CMOS Charge pumps. The performance of charge pumps mainly depends on the ability to efficiently generate high output voltages from the low input supply voltage. The shoot through current and the switching noise are being reduced by the proposed CMOS charge pump circuit. It is also used to improve the large driving capability and for eliminating the reversion loss. The proposed cross coupled charge pump has provided up to 8% percentage efficiency as compared with the conventional CMOS charge pump. The CMOS charge pump (CP) is an integral part in the phase-locked loops. CMOS charge pump circuits used for generating a high voltage from a low supply voltage are used in ICs, such as flash memories, smart power, dynamic random access memories (DRAMs), LEDs and LCD drivers(7). A charge pump is used in DRAMs to generate word-line voltage higher than the su...
High Performance CMOS Charge Pumps for Phase-locked Loop
Transactions on Electrical and Electronic Materials, 2015
Phase-locked-loops (PLL) have been employed in high-speed data transmission systems like wireless transceivers, disk read/write channels and high-speed interfaces. The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs. This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance. The CP architecture is evaluated by its current matching, charge sharing, voltage output range, linearity and power consumption characteristics. This review shows that the CP has significant impact on the quality performance of CP PLLs.
Charge Pump, Loop Filter and VCO for Phase Lock Loop Using 0.18µm CMOS Technology
This paper presents a Low power charge pump, second order low pass filter and voltage controlled oscillator for low power phase lock loop. The paper contains the detailed circuit diagram of charge pump, loop filter and voltage control oscillator with 1.8v power supply. The design has been realized using 0.18um CMOS technology. Here current starved voltage control oscillator is use for phase lock loop.
A CMOS Charge Pump Circuit with Short Turn-on Time for Low-spur PLL Synthesizers
JSTS:Journal of Semiconductor Technology and Science
A charge pump circuit with very short turn-on time is presented for minimizing reference spurs in CMOS PLL frequency synthesizers. In the source switching charge pump circuit, applying proper voltages to the source nodes of the current source FETs can significantly reduce the unwanted glitch at the output current while not degrading the rising time, thus resulting in low spur at the synthesizer output spectrum. A 1.1-1.6 GHz PLL synthesizer employing the proposed charge pump circuit is fabricated in 65 nm CMOS. The current consumption of the charge pump is 490 mA from 1 V supply. Compared to the conventional charge pump, it is shown that the reference spur is improved by 7.5 dB through minimizing the turn-on time. Theoretical analysis is described to show that the measured results agree well with the theory.
A Precise SystemC-AMS Model for Charge Pump Phase Lock Loop Verified by its CMOS
SystemC-AMS as an extension of SystemC provides the essential capability to describe a mixed-signal heterogeneous system, so that a virtual-prototype model can be generated to help analyze a whole mixed-signal system and further guide the circuit design. This paper presents a novel SystemC-AMS model of a high frequency Charge Pump Phase Lock Loop, including digital models like Phase/Frequency Detector and clock N-divider, and analog models like Charge Pump, Low Pass Filter and Voltage Controlled Oscillator. In order to prove the model's accuracy, the SPICE simulation result from the corresponding CMOS circuits based on the same structure of these models is used for comparison, and PLL SystemC-AMS model is validated.
Design and noise analysis of a fully-differential charge pump for phase-locked loops
Journal of Semiconductors, 2009
A fully-differential charge pump (FDCP) with perfect current matching and low output current noise is realized for phase-locked loops (PLLs). An easily stable common-mode feedback (CMFB) circuit which can handle high input voltage swing is proposed. Current mismatch and current noise contribution from the CMFB circuit is minimized. In order to optimize PLL phase noise, the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle. The calculation result agrees well with the simulation. Based on the noise analysis, many methods to lower output current noise of the FDCP are discussed. The fully-differential charge pump is integrated into a 1-2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18 µm process. The measured output reference spur is-64 dBc to-69 dBc. The in-band and out-band phase noise is-95 dBc/Hz at 3 kHz frequency offset and-123 dBc/Hz at 1 MHz frequency offset respectively.
Microelectronics Journal, 2013
The charge pump (CP) circuit is one of the main building block in a phase-locked loop (PLL) based frequency synthesizers. In conventional CMOS charge pump circuits, there are some non-ideal effects such as clock feed through, current mismatch and charge sharing which result in a phase offset in phaselocked loop circuits. This paper presents a new charge pump circuit in 0:18 μm CMOS technology, which greatly reduces the mismatch of current between two branches of the cascode current mirror. By using this proposed architecture, the mismatching between the UP/DN current of the CP can be achieved with less than 0.065% from post-layout simulation. As a result the spur and also the overall phase noise of the PLL are reduced. The charge pump output voltage range is 0.40-1.25 V. Additionally, the proposed circuit has wide output voltage swing and high output resistance, which ensures its good performance under very low power supply. Further, this CP circuit is incorporated with a new switching circuit to eliminate the clock feed through and charge injection error.
Analysis of Charge-Pump Phase-Locked Loops
2004
In this paper, we present an exact analysis for thirdorder charge-pump phase-locked loops using state equations. Both the large-signal lock acquisition process and the small-signal linear tracking behavior are described using this analysis. The nonlinear state equations are linearized for the small-signal condition and the-domain noise transfer functions are derived. A comparison to some of the existing analysis methods such as the impulse-invariant transformation and-domain analysis is provided. The effect of the loop parameters and the reference frequency on the loop phase margin and stability is analyzed. The analysis is verified using behavioral simulations in MATLAB and SPECTRE.