SIMULATIVE & COMPARATIVE STUDY OF CMOS TECHNIQUES USING FULL ADDER (original) (raw)

Simulative & Comparative Study of Cmos Techniques Using Full Adder 1 Shikha Singhal

Low power has emerged as a principal theme in today's electronic industry. Reduction of power consumption makes a device more reliable and efficient. The minimum amount of power consumption is the main concern for an efficient result. As an outcome, CMOS technology are best known for low power consumption devices. In this paper, designing techniques have been compared for minimum power dissipation in the circuits. A comparison between conventional static transistor, CPL (complementary pass transistor) & DPL (double pass transistor) has been performed. Delay, transistor count & power consumption are the factors through which we can drive our techniques in a better way.

DESIGN OF LOW-POWER FULL ADDER IN 0.18 µm CMOS TECHNOLOGY

With the increase in device integration level and the growth in complexity of Integrated circuits, small delay and low power dissipation become important parameters as these increases performance and portability. Battery storage is limited, to extend battery life; low power operation is the primary requirement in integrated circuits. Furthermore, high speed and multiple parallel applications need high computing power, placing greater demands on energy storage elements within the system. Large power dissipation in high performance digital systems requires large size heat sinks. These off chip component makes chip bulky and require large space. Secondly, extra heat in integrated circuit degrades the system performance. The full adder (FA) is a very important and basic building block in Arithmetic and Logic unit (ALU) of digital processor. The most widely accepted metrics to measure the quality of a digital circuit or to compare various circuit styles is power delay product. Further, Portability imposes a strict limitation on power dissipation while needs more computational speeds. The reduced power consumption and the improved speed require optimizations at all levels of the design procedure.

IJERT-Power Efficient CMOS Full Adders with Reduced Transistor Count

International Journal of Engineering Research and Technology (IJERT), 2014

https://www.ijert.org/power-efficient-cmos-full-adders-with-reduced-transistor-count https://www.ijert.org/research/power-efficient-cmos-full-adders-with-reduced-transistor-count-IJERTV3IS031276.pdf In this Paper, a CMOS Full Adder is designed using Tanner EDA Tool based on 0.25μm CMOS Technology. Using Tanner software tools, schematic and simulations of CMOS full adder are designed and presented, which helps to obtain design constraints. As part of this we have performed the simulation of CMOS full adder using T-SPICE of Tanner EDA. This paper also proposes a new 3T-XOR gate with significant area and power savings. A new eight transistors one bit full adder based on 3T-XOR gate is presented. Simulations results utilizing standard 0.25μm CMOS technology illustrate a significant improvement in terms of number of transistors, chip area and propagation delay.

Analysis of Different CMOS Full Adder Circuits Based on Different Parameter for Low Voltage

International journal of engineering research and technology, 2018

The demand for portable consumer electronics products is increasing at extremely high rate in recent years; therefore development of low-power VLSI circuits is essential. To achieve this objective a lot of innovative work has been done in this field, many innovative designs for basic logic functions have appeared. Various adders are used for implementing these logic functions which are most important components in digital design. The performance of these full adders can be measured in terms of propagation delay, power dissipation and power delay product. In this paper the performance of eleven different 1-bit full adder cells based on different logic styles are evaluated. The framework includes evaluation performance of different logic styles including an input test pattern which are analyzed with respect to power, delay and power-delay product. Evaluating the performance of a full adder cell is categorized on the basis of three different types of analysis: 1. Comparison of full add...

Low Power Full Adder Circuit ImplementedIn Different Logic

International Journal of Innovative Research in Science, Engineering and Technology, 2014

The aim of this paper is to evaluate the performance of One-bit full adder cell. Different Full Adder cell with conventional static CMOS Adder is being compared. Each Cell showed different power consumption and Delay. Power consumption and speed are two important but conflicting design aspects; hence a better way to evaluate circuit performance is power delay product (PDP).The driving capability of a full adder is very important, because, full adders are mostly used in cascade configuration, where the output of one provides the input for other. Here, we have given a brief description of the evolution of full adder circuits in terms of lesser power consumption, higher speed and lesser chip size. Starting from the most conventional 28 transistor full adder we have gradually studied full adders consisting of as less as 14 transistors (14 T), 16 transistors (16T), CMOS Transmission Gate (TG), Complementary Pass-transistor Logic (CPL), Gate Diffusion Input (GDI) and Static Energy Recover...

Low Power-Delay-Product CMOS Full Adder

2015

This paper shows an effective and improved circuit design for 1-bit full adder circuit with lesser energy required. The circuit is designed using total number of 9 transistors. The proposed circuit performance better in terms of power, delay, power delay product which is very easily shown by the simulation results. There is comparison of performance among proposed circuit with other pre-exist circuits in various literatures and this comparison shows higher reduction in Power-Delay-Product (pJ) of our proposed design. It has remarkably improved power consumption and temperature sustainability when compared with existing design. BSIM standard models are used for simulations. The proposed design gives faster response for the carry output and can be used to reduce more at higher temperature.

A Review of 1-Bit Full Adder Design Using Different Dynamic CMOS Techniques

2021

The Domino CMOS Logic Circuits are famously utilized in Very Large Scale Integrated (VLSI) structure. To design a VLSI circuit having low power and fast execution or high speed is the most testing task. By and by, one of the main goals is low power VLSI circuits with high speed. Full Adders are mainly used in various circuits which can perform various errands like development, duplication, division etc. In this manner it will diminish the force usage in full adders expects an enormous part of VLSI circuits having low power. In this paper, domino logic is used to manage a stable, particularly improved response for two constraints in full adder circuits i.e. power and delay. We review the Power, Delay and Power Delay Product (PDP) of 22T Domino Full Adder, 27T Domino Full Adder and 28T Static Full Adder. In this we also review these 3 circuit on the basis of different technology nodes or the feature length i.e. 45nm, 90nm and 180nm.

DESIGN OF ENERGY-EFFICIENT FULL ADDER USING HYBRID-CMOS LOGIC STYLE Copyright IJAET

We present new designs for full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness and low energy operations guided our research to explore hybrid- CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full adder designs can be conceived. The new full adder is based on XOR-XOR Hybrid CMOS model that gives XOR and XOR full swing output simultaneously. This circuit’s outperforms its counterparts showing 4%-31% improvement in power dissipation and delay. The output stage also provides good driving capability and no buffer connection is needed between cascaded stages. During our experiments, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adders are energy efficient and outperform several standard full adders without trading of driving capabilities and reliabilities. The new full-adder circuits successfully operate at low voltages with excellent signal integrity and driving capability. The new adders displayed better performance as compared to the standards full adder. The problem we face during the experiment leads us to different zones where efficient circuit can be developed using this new full adder.

Design of Energy-Efficient Full Adders Using Hybrid-CMOS Logic Style

IJAET Jan-2012 ISSN, 1963

We present new designs for full adder featuring hybrid-CMOS design style. The quest to achieve a gooddrivability, noise-robustness and low energy operations guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full adder designs can be conceived. The new full adder is based on XOR-XOR Hybrid CMOS model that gives XOR and XOR full swing output simultaneously. This circuit's outperforms its counterparts showing 4%-31% improvement in power dissipation and delay. The output stage also provides good driving capability and no buffer connection is needed between cascaded stages. During our experiments, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adders are energy efficient and outperform several standard full adders without trading of driving capabilities and reliabilities. The new fulladder circuits successfully operate at low voltages with excellent signal integrity and driving capability. The new adders displayed better performance as compared to the standards full adder. The problem we face during the experiment leads us to different zones where efficient circuit can be developed using this new full adder.

PERFORMANCE ANALYSIS OF LOW POWER FULL ADDER CELLS USING 45NM CMOS TECHNOLOGY

International Journal of Microelectronics Engineering (IJME), 2015

This paper puts forward different low power adder cells using different XOR gate architectures. Adder plays an important role in arithmetic operation such as addition, subtraction, multiplication, division etc. The optimization and characterization of such low power adder designs will aid in comparison and choice of adder modules in system design. A comparative analysis is performed for the power, delay, and power delay product (PDP) optimization characteristic& deals with the design of five adder cells using transistors and schematic structure using CADENCE tool. 10 transistor adder circuits shows the least power consumption with others. Simulations are performed by using Cadence Design tools using 45nm CMOS technology. The four adder cell module proposed here demonstrates their advantages in comparison with Static Energy Recovery Full (SERF), including lower power consumption, smaller area, and higher speed at different frequencies. Keywords Low power, Static Energy Recovery Full Adder (SERF), 45 nm technology, power delay product (PDP).