Ion-bombardment induced morphology change of device related SiGe multilayer heterostructures (original) (raw)

Highly-ordered SiGe-islands grown by dislocation patterning using ion-assisted MBE

Surface Science, 2007

Fabrication of device structures based on laterally self-ordered systems without the use of expensive and time-consuming nanolithography could have undoubted advantages. For such applications, it is proposed to use misfit dislocation networks from partially relaxed SiGe layers on (1 0 0) Si substrate as a template for the growth of highly ordered SiGe islands. Ion bombardment during molecular beam epitaxy of metastable SiGe layers leads to such a partial relaxation by misfit dislocation networks. The ions are generated by the interaction of the evaporated Si flux with the electrons in an electron beam evaporator, which causes a partial ionization of Si atoms in the molecular beam. We demonstrate by atomic force microscopy that subsequent growth of SiGe on such relaxed SiGe (25-50% Ge) layers leads to the formation of uniform three-dimensional islands highly ordered in h1 1 0i directions.

Ion assisted MBE growth of SiGe nanostructures

Thin Solid Films, 1998

The bombardment of thin SiGe buffers with 1-keV Si 1 ions during molecular beam epitaxial growth is a possible way for the injection of point defects in order to promote the relaxation and to reduce the dislocation density. For this purpose, the e-beam evaporator was optimized by increasing the emission current and decreasing the energy of the impinging electrons to create a high density Si 1 ion¯ux in our MBE system. To the isolated substrate holder a potential up to several kilovolts can be applied to direct, focus and accelerate Si 1 ions. A high ef®ciency Ge effusion cell ensures stable and controllable Ge¯uxes for growth rates up to 2.5 A Ê /s. Under these conditions, several sets of thin SiGe layers (65±300 nm) containing from 23 to 100% of Ge were grown and investigated comparatively with reference samples deposited without ions at 6508C. By the`ion growth program', after the deposition of Si buffers, SiGe layers were grown in three stages. The ®rst part of the layer (e.g. 1/8 of the nominal thickness) and the last one (e.g. 5/8 of the thickness) were grown without ion bombardment. The second part (e.g. 2/8 of the thickness) was deposited under 1-keV accelerated Si 1 ion bombardment. Ge content was kept constant during all three stages. Sharp interfaces and uniform Ge pro®les were shown by SIMS. Strain relaxation in the thicker layers is nearly 100% as proven by XRD. In thin pseudomorphic layers with low Ge content, a bombardment may result in nucleation of stacking faults shown by TEM. AFM and preferential chemical etching of relaxed ion bombarded layers have shown higher surface smoothness and a reduction of etch pit densities. q 1998 Elsevier Science S.A. All rights reserved.

New strategies for producing defect free SiGe strained nanolayers

Scientific reports, 2018

Strain engineering is seen as a cost-effective way to improve the properties of electronic devices. However, this technique is limited by the development of the Asarro Tiller Grinfeld growth instability and nucleation of dislocations. Two strain engineering processes have been developed, fabrication of stretchable nanomembranes by deposition of SiGe on a sacrificial compliant substrate and use of lateral stressors to strain SiGe on Silicon On Insulator. Here, we investigate the influence of substrate softness and pre-strain on growth instability and nucleation of dislocations. We show that while a soft pseudo-substrate could significantly enhance the growth rate of the instability in specific conditions, no effet is seen for SiGe heteroepitaxy, because of the normalized thickness of the layers. Such results were obtained for substrates up to 10 times softer than bulk silicon. The theoretical predictions are supported by experimental results obtained first on moderately soft Silicon ...

Interplay of dislocation network and island arrangement in SiGe films grown on Si(001)

Thin Solid Films, 2000

A two-temperature process has been applied to grow 80-nm Si,,,Ge,,, films on Si(OO1) by molecular-beam epitaxy (MBE). The first 30 nm were deposited at a reduced temperature of only 150-200°C (low-temperature stage). The subsequent growth was performed at 550°C, the temperature range conventionally applied for SiGe MBE. Using atomic-force microscopy, we observed that the misfit dislocation network introduced during sample heating after the low-temperature (LT) stage guides the arrangement of {105$-faceted pyramid-like islands. In the case of a very narrow dislocation network ~ induced by ion-assisted growth during the LT stage ~ a checkerboard array of {105$-faceted pits and pyramids evolves with a 'lattice constant' of approximately 200 nm. 0 2000 Elsevier Science B.V. All rights reserved. microscopy 0040-6090/00/$ -see front matter 0 2000 Elsevier Science B.V. All rights reserved. PII: S 0 0 4 0 -6 0 9 0 ( 0 0 ) 0 1 4 6 3 -2

SiGe nanostructures: new insights into growth processes

Journal of Physics: Condensed Matter, 2002

During the last decade, Si/Si 1−x Ge x heterostructures have emerged as a viable system for use in CMOS technology with the recent industrial production of heterojunction bipolar transistor-based integrated circuits. However, many key problems have to be solved to further expand the capabilities of this system to other more attractive devices. This paper gives a comprehensive review of the progress achieved during the last few years in the understanding of some fundamental growth mechanisms. The discrepancies between classical theories (in the framework of continuum elasticity) and experimental results are also specially addressed. In particular, the major role played by kinetics in the morphological evolution of layers is particularly emphasized. Starting from the unexpected differences in Si 1−x Ge x morphological evolution when deposited on (001) and on (111), our review then focuses on: (1) the strain control and adjustment (from fully strained to fully relaxed 2D and 3D nanostructures)in particular, some original examples of local CBED stress measurements are presented; (2) the nucleation, growth, and self-assembly processes, using self-patterned template layers and surfactant-mediated growth; (3) the doping processes (using B for type p and Sb for type n) and the limitations induced by dopant redistribution during and after growth due to diffusion, segregation, and desorption. The final section will briefly address some relevant optical properties of Si 1−x Ge x strained layers using special growth processes. (Some figures in this article are in colour only in the electronic version) (HBT). The main reason is that it presents a minimum additional cost to CMOS and a very simple design with a narrow Si 1−x Ge x base layer inserted into a bipolar BiCMOS fabrication process. However, even if this technology is quite mature, the device characteristics obtained in production lines are much less good than those demonstrated for research devices. This result has not been explained so far, but the high thermal budget, used in present CMOS production, is assumed to have the major detrimental effect. Indeed, it causes strain relaxation (by dislocation nucleation and also by interdiffusion of Si/Si 1−x Ge x), dopant diffusion, interface roughening, and Ge clustering. All these phenomena are well known to degrade the electrical properties of HBTs. Recent research developments also focus on other attractive devices such as the p-type Si 1−x Ge x MOSFET, since p channels represent so far the major limiting factor in CMOS performance. Indeed, the mobility of Si 1−x Ge x p MOSFET is only 20% larger than those of conventional transistors. This is attributed to parallel conduction due to the small band offset of Si 1−x Ge x channels that contain low Ge content. Further improvements would then rely on an increase of the Ge content to increase the band offset. This is expected to give stronger transfer and confinement of the carriers, preventing parallel conduction from taking place. However, this faces serious problems, since at large Ge contents, both the critical thickness of dislocation nucleation (h cr) and the critical thickness of 2D-3D growth transition (H S K) are very low. A good control and understanding of stress relaxation in 2D wells is consequently a major issue to address for these devices. Recently, the most striking performances have been reported for Si 1−x Ge x modulationdoped field effect transistors (MODFETs) grown on virtual substrates (fully relaxed by a network of misfit dislocations (MDs)) yielding faster transistors than any other p-channel transistor in the literature [1]. In spite of the high mobility achieved, the overall success of Si 1−x Ge x MODFETs has so far been limited because of the high dislocation density and the poor surface morphology (cross-hatch pattern) which impair further the processing of the structures. Since the cross-hatch pattern originates from the MDs lying mainly in the graded buffer layer, the search for new processes of fabrication of the relaxed buffer layer is a hot topic. Finally for the future, alternative routes to CMOS technology should also be developed for feature sizes approaching 50-30 nm. A new generation of nanometric devices should then be found as a matter of urgency, in order to permit the current scaling trend to continue, following the conventional CMOS approach. For this reason, many new quantum device concepts have recently been reported in the literature. However, there are major bottlenecks in the development of these emerging devices relating to:

Ion-assisted MBE for misfit-dislocation templates serving ordered growth of SiGe islands

Thin Solid Films, 2008

In this work, Si + ions generated by the electron-beam evaporator are employed to influence strain and morphology of MBE-grown SiGe layers on Si (100) substrates. Strain relaxation of SiGe layers and modified surface morphology are attained by ion bombardment at reduced growth temperature. A study on the influence of ion energy (0-1000 eV) and density on both degree of relaxation and surface morphology is performed. Regular misfit-dislocation networks and a specific surface morphology are observed when the in situ ion bombardment at reduced temperatures leads to a degree of relaxation around 25%. This surface morphology shows uniform shallow pyramids ordered in b110N directions which provide a template favourable for nanomagnets and other opto-and nanoelectronic applications.

Dislocation engineering in SiGe heteroepitaxial films on patterned Si (001) substrates

Applied Physics Letters, 2011

We demonstrate dislocation engineering without oxide masks. By using finite element simulations we show how nanopatterning of Si substrates with ͕111͖ trenches provides anisotropic elastic relaxation in a SiGe film, generates preferential nucleation sites for dislocation loops, and allows for dislocation trapping, leaving wide areas free of threading dislocations. These predictions are confirmed by atomic force and transmission electron microscopy performed on overcritical Si 0.7 Ge 0.3 films. These were grown by molecular beam epitaxy on a Si͑001͒ substrate patterned with periodic arrays of selectively etched ͕111͖-terminated trenches.

Reduced Pressure–Chemical Vapour Deposition of Si/SiGe heterostructures for nanoelectronics

Materials Science and Engineering: B, 2008

We have first of all quantified the impact of pressure on Si and SiGe growth kinetics. Definite growth rate and Ge concentration increases with the pressure have been evidenced at low temperatures (650-750 • C). By contrast, the high temperature (950-1050 • C) Si growth rate either increases or decreases with pressure (gaseous precursor depending). We have then described the selective epitaxial growth process we use to form Si or Si 0.7 Ge 0.3 :B raised sources and drains on ultra-thin patterned Silicon-On-Insulator (SOI) substrates. We have afterwards presented the specifics of SiGe virtual substrates and of the tensile-strained Si layers grown on top (used as templates for the elaboration of tensily strained-SOI wafers). The tensile strain, which can be tailored from 1.3 up to 3 GPa, leads to an electron mobility gain by a factor of 2 in n-Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) built on top. High Ge content SiGe virtual substrates can also be used for the elaboration of compressively strained Ge channels, with impressive hole mobility gains (×9) compared to bulk Si. After that, we have described the main structural features of thick Ge layers grown directly on Si (that can be used as donor wafers for the elaboration of GeOI wafers or as the active medium of near infrared photo-detectors). Finally, we have shown how Si/SiGe multilayers can be used for the formation of high performance 3D devices such as multi-bridge channel or nano-beam gate-all-around FETs, the SiGe sacrificial layers being removed thanks to plasma dry etching, wet etching or in situ gaseous HCl etching.

Low-temperature strain relaxation in SiGe/Si heterostructures implanted with Ge+ ions

Materials Science and Engineering: B, 2003

Pseudomorphic Si 0.76 Ge 0.24 /Si heterostructures grown by molecular beam epitaxy were implanted with Ge ' ions at 400 8C in such a way that an ion-damaged region was located below the SiGe/Si interface. The effect of Ge '-ion irradiation on strainrelaxation rate and defect structure in the heterostructures was studied by transmission electron microscopy (TEM), X-ray diffraction (XRD), atomic force microscopy (AFM), and low-temperature photoluminescence (PL). It was found that annealing at a temperature as low as 600 8C resulted in very high degree of strain relaxation, while density of threading dislocations was low (B/ 10 5 cm (2). The enhanced strain relaxation was attributed to the fact that complexes of point defects produced by the heavy-ion implantation at the elevated temperature acted as nucleation sites for dislocations. The obtained results allowed us to propose a method for preparation of thin highly relaxed SiGe layer with low threading dislocation density and good surface morphology.