A Low-Power mmWave CML Prescaler in 65nm SOI CMOS Technology (original) (raw)

CMOS LOW POWER, HIGH SPEED DUAL-MODULUS 32/33 PRESCALER IN SUB-NANOMETER TECHNOLOGY

IJSTE, 2014

Frequency synthesizer is one of the important elements for wireless communication application. The speed of VCO and prescaler determines how fast the frequency synthesizer is. A dual modulus prescaler contains logic gates and flip-flops. To fulfill the need of high frequency and low voltage circuit suitable flip-flops must be selected. The prescaler is a circuit employed in high frequency synthesizer designs. In the proposed circuit the technique called the True Single Phase Clock (TSPC) technique, was applied.Divide-by-2/3 prescaler is implemented by TSPC flip-flops. Divide by 32/33 prescaler is implemented by choosing various combinations of 2/3 prescaler and flip-flops. The DMP circuit implemented in 45nm CMOS process and simulation was carried out in Tanner EDA tool. The simulation results are provided. It consumes 86.42µWwith 1V power supply voltage at 2.4GHz.

65nm SOI CMOS SoC Technology for Low-Power mmWave and RF Platform

2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2008

An RF and mmWave platform developed in 65nm SOI CMOS technology is presented. The SOI FET performance in a wired cell is measured up to f T =300GHz and 200GHz for NFET and PFET. Ring oscillator records 3.6psec minimum inverter stage delay. Back-end-of-line Vertical Native Capacitor (VNCAP) and on-chip inductor performances are reported. The performance scaling trends of mmWave PLL front-end components are presented.

Performance and Yield Optimization of mm-Wave PLL Front-End in 65nm SOI CMOS

2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2007

A combination of LC-VCO and 2:1 CML fREF static frequency divider has been fabricated in 65nm SOI L CMOS technology and operates at 70GHz. A cascoded buffer l amplifier is used in VCO-to-divider connection to AMP PLL Back-End compensate for the power losses caused by interconnect parasitics, and inductive peaking is employed for bandwidth Primary CMOS Sub enhancement. The bias condition of the frequency divider DiVider (a) has been tuned to find an optimal bias point in existence of VCO and frequency divider operating range variation. The PLL Front-End 200fF VCTRL VNCAP fDIV inter-die variation of VCO and divider performance LT ct Static variations over a wafer and their correlation have been VC V kf ML DivideL estimated.

New CML latch structure for high speed prescaler design

Canadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No.04CH37513)

This paper emphasizes on the design and analysis of Current Mode Logic latches and fheir application in a frequency prescaler. Operation of a conventional CML latch is analyzed and a clock feedback structure is proposed for increased stabilig with reduced delay parameters. A low power design technique is presented for Currenf Mode Logic j?equency prescalers, which allows the Master and Slave latches to be merged together so that they use a single current source. This significantly reduces the power consumption and area and also offers lower terminal capacitances resulting in faster circuit operation.

Design considerations in a BiCMOS dual-modulus prescaler

2002 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.02CH37280)

Design considerations in a dual modulus divide by 32/33 prescaler with a 0.6pm BiCMOS process are presented. Care was taken to design the ECL-based circuits to operate with as low supply voltage and current consumption as possible. The phase noise contribution of the integrated bandgap bias network is demonstrated through simulations. The tradeoff between the power consumption and the phase noise is pointed out and some guidelines are provided to improve the noise performance. Measurements confirm the hnctionality of the prescaler with a 2.5V supply drawing around 2.3mA at 2.35 GHz with an input sensitivity between-24dBm and l2dBm. The circuit operates with a supply voltage down to 2.1V but with limited input sensitivity.

A 1-GHz/0.9-mW CMOS/SIMOX divide-by-128/129 dual-modulus prescaler using a divide-by-2/3 synchronous counter

IEEE Journal of Solid-State Circuits, 1993

This paper presents an extremely low-power CMOS/SIMOX divide-by-128/129 dual-modulus prescaler. While operating at up to 1 GHz and dissipating merely 0.9 mW at a supply voltage of 1 V, it is capable of 2-GHz performance with dissipation of 7.2 mW at 2 V. This superior performance is primarily achieved by using an advanced ultrathin-film CMOS/SIMOX process technology combined with a new circuit configuration that uses a divide-by-2/3 synchronous counter. Using these same technologies, a single-chip CMOS PLL LSI that uses the developed prescaler is also fabricated. This CMOS PLL LSI can operate at up to 2 GHz while dissipating only 8.4 mW at a supply voltage of 2 V. Even at a lower supply voltage of 1.2 V, 1-GHz operation can be obtained with a corresponding power consumption of merely 1.4 mW. These results indicate that the high-speed and very-low-power features of CMOS/SIMOX technology could have an important impact on the development of future personal communication systems.

Low-phase-noise 54GHz quadrature VCO and 76GHz/90GHz VCOs in 65nm CMOS process

2014 IEEE Radio Frequency Integrated Circuits Symposium, 2014

This paper presents new circuit topologies and design techniques for low-phase-noise CMOS mmWave Quadrature VCO (QVCO) and VCOs. A transformer coupling with extra phase shift is proposed in QVCO to decouple the tradeoff between phase noise (PN) and phase error and improve the PN performance. This technique is demonstrated in a mmWave QVCO with a measured PN of -119.2dBc/Hz at 10MHz offset of a 56.2GHz carrier and a tuning range of 9.1% (FOM T of -179dBc/Hz). To our best knowledge, this QVCO has the lowest PN at 10MHz offset among all the QVCOs around 50-60GHz frequency range. In addition, an inductive divider feedback technique is proposed in VCO design to improve the transconductance linearity, resulting in larger signal swing and lower PN compared to the conventional LC VCOs. The effectiveness of this approach is demonstrated in a 76GHz VCO and a 90GHz VCO, both fabricated in a 65nm CMOS process, with an FOM T of 173.6dBc/Hz and 173.1dBc/Hz, respectively. Index Terms -VCO, quadrature VCO (QVCO), phase noise, transformer, transconductance linearization.

Fully integrated 5.35-GHz CMOS VCOs and prescalers

IEEE Transactions on Microwave Theory and Techniques, 2001

Two 5.35-GHz monolithic voltage-controlled oscillators (VCOs) and two prescalers have been fabricated in a digital 0.25m CMOS process. One VCO uses p + /n-well diodes, while the other uses MOS varactors. of 57 at 5.5 GHz and 0-bias (low-condition) for a p + /n-well varactor has been achieved. For an MOS varactor, it is possible to achieve a quality factor of 140 at 5.5 GHz. The tuning ranges of the VCOs are 310 MHz, and their phase noise is 116.5 dBc/Hz at a 1-MHz offset while consuming 7 mW power at DD = 1 5 V. The low phase noise is achieved by using only PMOS transistors in the VCO core and by optimizing the resonator layout. The prescalers utilize a variation of the source-coupled logic. The power consumption is 4.1 mW at 1.5-V DD and 5.4 GHz. By widening the transistors in the first three divide-by-two stages, the maximum operating frequency is increased to 9.96 GHz at DD = 2.5 V. (S'98) received the B.S. degree (with highest honors) and the M.Eng. degree in electrical engineering from the University of Florida, Gainesville, in 1996 and 1998, respectively, where he is currently pursuing the Ph.D. degree in electrical engineering.

Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler

IEEE Transactions on Microwave Theory and Techniques, 2006

The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a prescaler is proposed and implemented using a CMOS technology. Compared with the existing design, a 25% reduction of power consumption is achieved. A divide-by-8/9 dual-modulus prescaler implemented with this divide-by-2/3 unit using a 0.18-m CMOS process is capable of operating up to 4 GHz with a low-power consumption. The prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications.