A sixth-order continuous-time bandpass sigma-delta modulator for digital radio IF (original) (raw)
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IEEE Journal of Solid-State Circuits, 2000
In this paper, the design of a continuous-time baseband sigma-delta (61) modulator with an integrated mixer for intermediate-frequency (IF) analog-to-digital conversion is presented. This highly linear IF 61 modulator digitizes a GSM channel at intermediate frequencies up to 50 MHz. The sampling rate is not related to the input IF and is 13.0 MHz in this design. Power consumption is 1.8 mW from a 2.5-V supply. Measured dynamic range is 82 dB, and third-order intermodulation distortion is 84 dB for two 6-dBV IF input tones. Two modulators in quadrature configuration provide 200-kHz GSM bandwidth. Active area of a single IF 61 modulator is 0.2 mm 2 in 0.35-m CMOS.
This paper examines the design and implementation of an eighth-order bandpass delta-sigma modulator. The design process is investigated from the signal flow graph level, through to the details of the switched capacitor implementation and layout considerations. Simulation results, highlighting the effects of process variation, are provided and the experimental performance of the modulator described. The modulator is implemented in a 0.8-m BiCMOS process and occupies an active area of 1.7 mm 2 . Operating from 6 6 62.5-V supplies, the fabricated prototype exhibits stable behavior and achieves a dynamic range of 67 dB over a 200-kHz bandwidth centered at the commonly used intermediate frequency of 10.7 MHz. This paper, therefore, demonstrates the viability of high-order singlebit bandpass delta-sigma modulation.
A 10.7-MHz IF-to-baseband /spl Sigma//spl Delta/ A/D conversion system for AM/FM radio receivers
IEEE Journal of Solid-State Circuits, 2000
61 modulation with integrated quadrature mixing is used for analog-to-digital (A/D) conversion of a 10.7-MHz IF input signal in an AM/FM radio receiver. After near-zero IF mixing to a 165 kHz offset frequency, the and signals are digitized by two fifth-order, 32 times oversampling continuous-time 61 modulators. A prototype IC includes digital filters for decimation and the shift of the near-zero-IF to dc. The baseband output signal has maximum carrier-to-noise ratios of 94 dB in 9 kHz (AM) and 79 dB in 200 kHz (FM), with 97 and 82 dB dynamic range, respectively. The IM3 distance is 84 dB at full-scale A/D converter input signal. Including downconversion and decimation filtering, the IF A/D conversion system occupies 1.3 mm 2 in 0.25-m standard digital CMOS. The 61 modulators consume 8 mW from a 2.5-V supply voltage, and the digital filters consume 11 mW.
I-bit sigma delta analog to digital converter for multistandard GSM/UMTS radio receiver
2004 IEEE International Conference on Industrial Technology, 2004. IEEE ICIT '04., 2004
This paper deals with specification and design methodology of Analog to Digital Converter (ADC) stage for high dynamic range wide band Multi-standard Radio receiver. To respect high resolution requirements a Sigma Delta (Σ∆) Σ∆) Σ∆) Σ∆) modulator based ADC is proposed. A High dynamic range low complexity 1-bit Sigma Delta modulator is designed to guarantee high linearity for GSM/UMTS signals. Hence, a stable 3 rd order 1-bit low-pass Σ∆ Σ∆ Σ∆ Σ∆ modulator is defined. Simulation results show more than 90 dB dynamic ranges for GSM and 60 dB for UMTS.
Delta-sigma modulators using frequency-modulated intermediate values
IEEE Journal of Solid-State Circuits, 1997
This paper describes a new first-and second-order delta-sigma modulator concept where the first integrator is extracted and implemented by a frequency modulator with the modulating signal as the input. The result is a simple delta-sigma modulator with no need for digital-to-analog converters, allowing straightforward multi-bit quantization. Without the frequency modulator, the circuit becomes a frequency-to-digital converter with delta-sigma noise shaping. An experimental first-and second-order modulator have been implemented in a 1.2-¼m standard digital CMOS process and the results confirm the theory. For the first-order modulator an input signal amplitude of 150mV resulted in a SQNR of ³115dB at 2MHz sampling frequency and signal bandwidth 500Hz.
Preliminary Design and Comparative Analysis Between Different DT Sigma-Delta Modulators
Sigma-Delta analog-to-digital converters (ADCs) are known for providing high resolutions when compared to other ADC architectures. They are composed of a sigma-delta modulator and a digital decimation filter. This work focuses is in the high-level design of discrete-time sigma-delta modulators (DT-SDMs) whereas the design and implementation of first and second-order modulators are analyzed using Matlab. A complete performance analysis of each modulator is described using the cascade of integrators in feedback (CIFB) structure. It is worth mentioning that our study has a focus on medium bandwidth (BW) applications, as such audio applications. Besides, we target low-voltage operations. This work is at an early stage, thus only first and second-order modulators are investigated. This work considers a BW of 24 kHz, a sampling frequency of 6.144 MHz, and oversampling (OSR) of 128. Index Terms-sigma-delta modulators, sigma-delta ADC, DT-SDM CIFB structure.
IEEE Journal of Solid-State Circuits, 2001
This paper examines the architecture, design, and test of continuous-time tunable intermediate-frequency (IF) fourth-order bandpass delta-sigma (BP 16) modulators. Bandpass modulators sampling at high IFs (200 MHz) allow direct sampling of the RF signal-reducing analog hardware and make it easier to realize completely software programmable receivers. This paper presents circuit design of and test results from continuous-time fourth-order BP 16 modulators fabricated in AlInAs/GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency () of 80 GHz and a maximum frequency of oscillation (MAX) of about 130 GHz. Operating from 5-V power supplies, a fabricated 180-MHz IF fourth-order 16 modulator sampling at 4 GS/s demonstrates stable behavior and achieves 75.8 dB of signal-to-(noise + distortion)-ratio (SNDR) over a 1-MHz bandwidth. Narrowband performance (1 MHz) performance of these modulators is limited by thermal/device noise while broadband performance (60 MHz) is limited by quantization noise. The high sampling frequency (4 GS/s) in this converter is dictated by broadband (60 MHz) performance requirements.
Design of Multi-bit Sigma-Delta Modulators for Digital Wireless Communications
The ever advance of CMOS digital circuit process leads to the trend of digitizing an analog signal and performing digital signal processing as early as possible in a signal processing system, which in turn leads to an increasing requirement on analog-to-digital converter (ADC). A wireless transceiver is a such kind of signal processing system. Conventional transceivers manipulate (filter, amplify and mix) the signal mostly in analog domain. Since analog filters are difficult to design on-chip, the system integration level is low. Modern transceivers shift many of these tasks to digital domain, where the filtering and channel selection can be realized more accurately and more compactly. However the price for the high integration level is the critical requirement on the ADC, because the simplified analog part sends not only the weak signal but also the unwanted strong neighboring channel to the ADC. In order to digitize the needed signal in the presence of strong disturbances, a high dynamic-range and high-speed ADC is needed.
A 480 MHz Band-Pass Sigma Delta Analog to Digital Modulator with Active Inductor Based Resonators
Lecture Notes in Electrical Engineering, 2013
This paper presents a 1.2 GHz continuous time 6 th order band-pass Sigma Delta Analog to Digital modulator in IBM 0.18 um CMOS technology. Traditional RLC circuits, with spiral inductors as resonators, were replaced with active inductor based resonators with negative impedance circuits to enhance the quality factor, reduce chip area and eliminate post processing needs. Simulink and Cadence simulation yield an enhanced SNDR of 75 dB and power consumption of 29 mW. The modulator occupies 0.9 mm 2 of chip area.
2004
This paper presents the design of a second order, single-bit, analog-to-digital, continuous-time Delta-Sigma Modulator (CT-M) that can be used in wireless CDMA receivers. The CT-M samples at 2 GHz, consumes 18 mW at 1.8 V and has a 79 dB signal-to-noise ratio (SNR) over a 1.23 MHz bandwidth. The CT-M was fabricated in a 0.18 m, 1poly, 6-metal, CMOS technology and has an active area of approximately 0.892 mm 2. The M's critical performance specifications are derived from the CDMA receiver specifications. Index Terms-Analog-digital conversion, Code division multiple access, Continuous time delta-sigma modulation, CMOS, High-speed integrated circuit I. INTRODUCTION Recently, a family of receiver architectures, often called digital radio receivers, has gained interest in the wireless communications industry. Such architectures include the zero intermediate frequency (IF) (ZIF) receiver and the complex low IF (CLIF) or Weaver architecture receiver [1]. Unlike superheterodyne architectures that perform channel filtering and automatic gain control (AGC) after the first down conversion and digitize the received signal after a second down conversion, digital radio architectures digitize the received signal after a single down conversion and perform AGC and channel filtering digitally. As a result, digital radio receivers rely mainly on digital circuitry, and can therefore be programmed to operate as multimode receivers. Also, because the density of digital circuitry is far greater than that of RF circuitry, digital radio receivers can be fabricated on a single