On-chip ramp generators for mixed-signal BIST and ADC self-test (original) (raw)
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IEEE Transactions on Very Large Scale Integration Systems, 2019
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On-chip generator of a saw-tooth test stimulus for ADC BIST
SOC Design Methodologies, 2002
In the context of analog BIST for A-to-D converters, this paper presents an implementation of an on-chip ramp generator. It is demonstrated that the proposed original adaptive scheme allows the internal generation of a highly saw-tooth signal with a very precise control of the signal amplitude. In addition, the implementation of the adaptive ramp generator exhibits a very low silicon area.
2006
This paper presents a low-cost low-power self-test design and verification of on-chip analog-to-digital converter (ADC) for system-on-a-chip (SoC) applications. A methodology for performing mixed-mode built-in self-test (BIST) simulation was performed along with the BIST architecture. The architecture presented allows for generation of analog test signals of frequency up to 600 MHz, using a 4-b 2.5 Gsamples/s current steering digital-to-analog converter (DAC). Both integral nonlinearity (INL) and differential nonlinearity (DNL) errors of test signals were obtained about 0.5 LSB by the sine wave histogram testing. The measured power dissipation for generated test signals of 600 MHz at the power supply of 1.2 V is about 5.32 mW. The current steering DAC achieves 22.3 dB of spur free dynamic range (SFDR) for 600 MHz signals
On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST
Journal of Electronic Testing, 2003
In the context of analog BIST for ADC, this paper presents two structures for the internal generation of a linear signal used with the histogram-based test technique. All of these structures use wide-swing current mirrors and an original adaptive system to make the generators less sensitive to process variations. The first structure allows us to generate high quality ramp signal.
High-Resolution ADC Linearity Testing Using a Fully Digital-Compatible BIST Strategy
IEEE Transactions on Instrumentation and Measurement, 2009
This paper proposes a digital-compatible built-in self-test (BIST) strategy for high-resolution analog-to-digital converter (ADC) linearity testing using only digital testing environments. The on-chip stimulus generator consists of three lowresolution and low-accuracy current steering digital-to-analog converters (DACs), which are area efficient and easy to design. The linearity of the stimuli is improved by the proposed reconfiguration technique. ADCs' outputs are evaluated by simple digital logic circuits to characterize the nonlinearities. The proposed BIST strategy is capable of characterizing ADC transition levels one by one with small hardware overhead. The testing performance is not sensitive to the mismatches and process variations, so that the analog BIST circuits can easily be reused without complex self-calibration. Simulation and experimental results show that the proposed circuitry and BIST strategy can test the INL k error of 12-bit ADCs to a ±0.15 least significant bit (LSB) accuracy level using only 7-bit linear DACs.
A fully digital-compatible BIST strategy for ADC linearity testing
2007 IEEE International Test Conference, 2007
Digital testing is much easier and cheaper than analog and mixed-signal testing because of the straightforward connections and the low-cost testers. This paper presents a fully digital-compatible built-in self-test strategy for ADC linearity testing using all digital testing environments. Onchip, low-accuracy DACs, which are area efficient and simple to design, are implemented as the stimulus generator. ADCs' nonlinearities are tested using a histogram-based method under the control of a logic block. The described strategy is capable of characterizing ADC transition levels one by one with small hardware overhead. Simulation and experimental results show that the proposed circuitry and BIST strategy can test the INL k error of 12-bit ADCs to ±0.2LSB accuracy level using only 7-bit linear DACs.
BIST and production testing of ADCs using imprecise stimulus
ACM Transactions on Design Automation of Electronic Systems, 2003
A new approach for testing mixed-signal circuits based upon using imprecise stimuli is introduced. Unlike most existing Built-In Self-Test (BIST) and production test approaches that require excitation signals that are at least 3 bits or more linear than the Device-Under-Test (DUT), the proposed approach can work with stimuli that are several bits less linear than the DUT. This dramatically reduces the requirements on stimulus generation for BIST applications and offers potential for using inexpensive signal generators in production test, or for testing DUTs that have a linearity performance exceeding that of the available test equipment. As a proof of concept, a histogram-based algorithm for linearity testing for Analog-to-Digital Converters (ADCs) has been proposed. It can estimate the Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) of an n -bit ADC by using a ramp signal of much less than n -bit linearity and a shifted version of the same nonlinear ramp as excitati...
A low-cost BIST architecture for linear histogram testing of ADCs
This paper investigates the viability of an ADC BIST scheme for implementing the histogram test technique. An original approach is developed to extract the ADC parameters from the histogram with a minimum area overhead. In particular, it is shown that the choice of a triangle-wave input signal combined with an appropriate time decomposition technique of the test procedure permits to drastically reduce the required on-chip hardware circuitry.
PWM-based test stimuli generation for BIST of high resolution ΣΔ ADCs
2008 Design, Automation and Test in Europe, 2008
A fully digital test stimuli generation and on-chip specifications evaluation for cheap, fast, though accurate testing of high resolution Σ∆ ADCs are here presented. Simulations and measurements showed a discrimination threshold on specification parameters up to-90dBc. The proposed method helps reduce the cost of ADC production test, to extend test coverage and to enable Built-In Self-Test and test-based self-calibration.