Achievable ADC Performance by Postcorrection Utilizing Dynamic Modeling of the Integral Nonlinearity (original) (raw)
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Two post processing algorithms for the correction of linearity errors that occur at Analog/Digital Converter (ADC) outputs are presented in this paper. One of these algorithms corrects periodic DNL errors lower than 1LSB (Least Significant Bit) while the second one can be used in any case of severe DNL variation at successive ADC output codes. Simulations based on the output of a real ADC show that the combination of these two algorithms can improve the Signal to Noise and Distortion Ratio (SNDR) by up to 6dB in an 8-bit ADC. These algorithms can be easily implemented in hardware using low complexity and die area digital circuits that can be placed between an ADC and the Signal Processing system that utilizes its output. Moreover, the output of these algorithms is in compressed form, leading to lower traffic at the output of the ADC and allowing the use of a serial interface for lower pin count. These linearity improvement algorithms are simulated in Matlab.