50μm pitch Pb-free micro-bumps by C4NP technology (original) (raw)
Related papers
C4NP - data for fine pitch to CSP flip chip solder bumping
2006 8th Electronics Packaging Technology Conference, 2006
To meet future requirements for cost, size, weight and electrical performance, microelectronic packaging is moving from wire bonds to solder bumps as the preferred method of interconnection from the device to the chip carrier or card. Flip chip in Package (FCiP) requires many small bumps on tight pitch whereas Wafer Level Chip Scale Packaging (WLCSP) typically requires much larger solder bumps on a greater pitch. Electroplating, solder paste printing and the direct attach of preformed solder spheres are technologies commonly used in volume production. Each of these techniques has limitations in scaling from fine pitch FCiP to WLCSP. Electroplating is better suited to fine pitch, whereas solder paste printing and solder sphere attachment work well for coarser pitches. C4NP (Controlled Collapse Chip Connection New Process) has proven to be suitable for this entire range of solder bump pitch. C4NP is a new solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into prefabricated and reusable glass templates (molds). The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. Filled mold and wafer are brought into close proximity/contact and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost, high yield and fast cycle time solution for both, fine-pitch FCiP as well as WLCSP bumping applications. This paper summarizes the latest manufacturing and reliability data for high-end logic device packaging using 300mm wafers bumped with C4NP. This includes reliability data for C4NP lead free solder bumped devices attached to organic chip carriers. Mold fill data for CSP type dimensions is included. Solder metrology data and yield information for fine pitch applications is summarized. Relevant process equipment technology and the unique requirements to run a high volume manufacturing C4NP process are reviewed. The paper also summarizes the C4NP manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques.
C4NP Technology for Lead Free Solder Bumping
2007 Proceedings 57th Electronic Components and Technology Conference, 2007
C4NP is a novel solder bumping technology developed by IBM that addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. It is a solder transfer technology where molten solder is injected into prefabricated and reusable glass molds. The glass mold contains etched cavities which mirror the bump pattern on the wafer. Filled mold and wafer are brought into close proximity/soft contact at reflow temperature and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. The simplicity of the process makes it a low cost, high yield and fast cycle time solution for bumping with a variety of high performance lead free alloys. The focus of this paper is on the mold fabrication, solder fill and inspection steps prior to solder transfer including high volume manufacturing tool designs. Yield improvements from the mold suppliers and mold specs are discussed. Finally, the results from a detailed cost model are reviewed. This cost model includes a comparison of C4NP versus alternative bumping techniques and includes capital, materials, and labor cost factors.
2009
In this paper we will present new cost-efficient solder bumping and adapted assembly technologies for the processing of flip-chips with a pitch of 100 µm or less and solder ball diameters of 60 µm or 50 µm, respectively. The wafer bumping has been realized using a highly efficient Wafer Level Solder Sphere Transfer (WLSST) process. This technology uses a patterned vacuum plate in order to simultaneously pick up all of the preformed solder spheres, optically inspect for yield, and then transfer them to the wafer at once. This paper will discuss this technology and the process parameters for producing fine pitch solder bumps. The flip-chips were assembled on special BT- and FR4-material using reflow soldering. Due to the large thermal expansion mismatch between substrate and chip, special epoxy based underfill has to be used in order to increase the long term reliability of the lead-free solder joints. The use of capillary flow as well as of no flow underfill and applicable design rul...
56th Electronic Components and Technology Conference 2006, 2006
To support the next generation highly integrated microsystem with 3-D silicon integration using fine pitch interconnection and Si carrier, we develop a fabrication and assembly process at IBM Research to produce solder microjoints (fine pitch flip-chip interconnections) for our systemon-package (SOP) technology. [1-3] We fabricate solder bumps with 25 µm (or less) in diameter on 50 µm pitch size, as well as 50 µm in diameter on 100 µm pitch size, at wafer level (200mm) by electroplating method. There are up to 10208 micro-bumps (25 µm) built on a chip surface less than 0.4 cm 2 . The process can be applied to various solder compositions, including eutectic SnPb, Pb-free (CuSn), AuSn and high Pb (3Sn97Pb) solders. The test matrix includes different solder/UBM (under bump metallization) combination.
Materials and Processes Issues in Fine Pitch Eutectic Solder Flip Chip Interconnection
IEEE Transactions on Components and Packaging Technologies, 2000
New product designs within the electronics packaging industry continue to demand interconnects at shrinking geometry, both at the integrated circuit and supporting circuit board substrate level, thereby creating numerous manufacturing challenges. Flip chip on board (FCOB) applications are currently being driven by the need for reduced manufacturing costs and higher volume robust production capability. One of today's low cost FCOB solutions has emerged as an extension of the existing infrastructure for surface mount technology and combines an under bump metallization (UBM) with a stencil printing solder bumping process, to generate mechanically robust joint structures with low electrical resistance between chip and board. Although electroless Ni plating of the UBM, and stencil printing for solder paste deposition have been widely used in commercial industrial applications, there still exists a number of technical issues related to these materials and processes as the joint geometry is further reduced. This paper reports on trials with electroless Ni plating and stencil paste printing and the correlation between process variables in the formation of bumps and the shear strength of said bumps at different geometries. The effect of precise control of tolerances in squeegees, stencils and wafer fixtures was examined to enable the optimization of the materials, processes, and tooling for reduction of bumping defects.
Demonstration of fine pitch FCOB (Flip Chip on Board) assembly based on solder bumps at Fermilab
Journal of Instrumentation, 2009
Bump bonding is a superior assembly alternative compared to conventional wire bond techniques. It offers a highly reliable connection with greatly reduced parasitic properties. The Flip Chip on Board (FCOB) procedure is an especially attractive packaging method for applications requiring a large number of connections at moderate pitch. This paper reports on the successful demonstration of FCOB assembly based on solder bumps down to 250 µm pitch using a SUESS MA8 flip chip bonder at Fermilab. The assembly procedure will be described, microscopic cross sections of the connections are shown, and first measurements on the contact resistance are presented.
Investigation of bump crack and deformation on Pb-free flip chip packages
2010
The demand for die to package interconnects free of Pb in the next generation flip chip packages requires a flux and underfill solution that meets package reliability requirements. Bump cracks and bump deformation were observed during temperature cycling on large body, full Pb-free ceramic flip chip BGA packages during initial package development. The phenomenon is considered unique in terms of its nature and failure mechanism. Traditional bump crack issues are concentrated at or near the silicon and underfill interfaces. In this case, cracks occurred within the bulk solder away from either silicon or substrate interface. Failed bumps also showed severe deformation. In addition, morphology differences in the underfill material surrounding the affected bumps provided important clues as to the nature of the failure mechanism. An extensive investigation to understand the root cause of the unique bump crack issue in the bulk solder, which covered both process and material-related factors, resulted in a clear understanding of the failure mechanism and the implementation of an effective solution to the problem. This manuscript describes the relationship of the flux residueunderfill interaction, the localized change in underfill properties due to the flux residues, and eventually the impact of this change on the bump integrity during package stressing. These findings made it possible to establish a good fluxunderfill selection methodology to achieve a robust Pb-free package solution that is being implemented in next generation flip chip products. Figure 1: Traditional bump crack
Design and Manufacturing of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications
Journal of Electronics Manufacturing, 2000
A novel and low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip is presented in this study. Emphasis is placed on the design, materials, process, manufacturing, and reliability of the micro VIP substrate of a chip scale package (CSP), and of the micro VIP CSP printed circuit board (PCB) assembly. Cross-sections of samples are examined for a better understanding of the solder bump, CSP redistribution, VIP, and solder joint. Non-linear finite element analyses are used to determine the stress and strain in the copper VIP and the solder joint. Time-dependent non-linear analysis is used to predict the thermal-fatigue life of the VIP solder joint.